141480Smckusick /* 241480Smckusick * Copyright (c) 1988 University of Utah. 3*63151Sbostic * Copyright (c) 1990, 1993 4*63151Sbostic * The Regents of the University of California. All rights reserved. 541480Smckusick * 641480Smckusick * This code is derived from software contributed to Berkeley by 741480Smckusick * the Systems Programming Group of the University of Utah Computer 841480Smckusick * Science Department. 941480Smckusick * 1041480Smckusick * %sccs.include.redist.c% 1141480Smckusick * 1253929Shibler * from: Utah $Hdr: grf_rbreg.h 1.9 92/01/21$ 1341480Smckusick * 14*63151Sbostic * @(#)grf_rbreg.h 8.1 (Berkeley) 06/10/93 1541480Smckusick */ 1641480Smckusick 1741480Smckusick /* 1841480Smckusick * Map of the Renaissance frame buffer controller chip in memory ... 1941480Smckusick */ 2041480Smckusick 2153929Shibler #include <hp/dev/iotypes.h> /* XXX */ 2253929Shibler 2341480Smckusick #define rb_waitbusy(regaddr) \ 2441480Smckusick while (((struct rboxfb *)(regaddr))->wbusy & 0x01) DELAY(100) 2541480Smckusick 2641480Smckusick #define CM1RED ((struct rencm *)(ip->regbase + 0x6400)) 2741480Smckusick #define CM1GRN ((struct rencm *)(ip->regbase + 0x6800)) 2841480Smckusick #define CM1BLU ((struct rencm *)(ip->regbase + 0x6C00)) 2941480Smckusick #define CM2RED ((struct rencm *)(ip->regbase + 0x7400)) 3041480Smckusick #define CM2GRN ((struct rencm *)(ip->regbase + 0x7800)) 3141480Smckusick #define CM2BLU ((struct rencm *)(ip->regbase + 0x7C00)) 3241480Smckusick 3341480Smckusick struct rencm { 3441480Smckusick u_char :8, :8, :8; 3541480Smckusick vu_char value; 3641480Smckusick }; 3741480Smckusick 3841480Smckusick struct rboxfb { 3941480Smckusick u_char filler1[1]; 4041480Smckusick vu_char reset; /* reset register 0x01 */ 4141480Smckusick vu_char fb_address; /* frame buffer address 0x02 */ 4241480Smckusick vu_char interrupt; /* interrupt register 0x03 */ 4341480Smckusick u_char filler1a; 4441480Smckusick vu_char fbwmsb; /* frame buffer width MSB 0x05 */ 4541480Smckusick u_char filler1b; 4641480Smckusick vu_char fbwlsb; /* frame buffer width MSB 0x07 */ 4741480Smckusick u_char filler1c; 4841480Smckusick vu_char fbhmsb; /* frame buffer height MSB 0x09 */ 4941480Smckusick u_char filler1d; 5041480Smckusick vu_char fbhlsb; /* frame buffer height MSB 0x0b */ 5141480Smckusick u_char filler1e; 5241480Smckusick vu_char dwmsb; /* display width MSB 0x0d */ 5341480Smckusick u_char filler1f; 5441480Smckusick vu_char dwlsb; /* display width MSB 0x0f */ 5541480Smckusick u_char filler1g; 5641480Smckusick vu_char dhmsb; /* display height MSB 0x11 */ 5741480Smckusick u_char filler1h; 5841480Smckusick vu_char dhlsb; /* display height MSB 0x13 */ 5941480Smckusick u_char filler1i; 6041480Smckusick vu_char fbid; /* frame buffer id 0x15 */ 6141480Smckusick u_char filler1j[0x47]; 6241480Smckusick vu_char fbomsb; /* frame buffer offset MSB 0x5d */ 6341480Smckusick u_char filler1k; 6441480Smckusick vu_char fbolsb; /* frame buffer offset LSB 0x5f */ 6541480Smckusick u_char filler2[16359]; 6641480Smckusick vu_char wbusy; /* window mover is active 0x4047 */ 6741480Smckusick u_char filler3[0x405b - 0x4048]; 6841480Smckusick vu_char scanbusy; /* scan converteris active 0x405B */ 6941480Smckusick u_char filler3b[0x4083 - 0x405c]; 7041480Smckusick vu_char video_enable; /* drive vid. refresh bus 0x4083 */ 7141480Smckusick u_char filler4[3]; 7241480Smckusick vu_char display_enable; /* enable the display 0x4087 */ 7341480Smckusick u_char filler5[8]; 7441480Smckusick vu_int write_enable; /* write enable register 0x4090 */ 7541480Smckusick u_char filler6[11]; 7641480Smckusick vu_char wmove; /* start window mover 0x409f */ 7741480Smckusick u_char filler7[3]; 7841480Smckusick vu_char blink; /* blink register 0x40a3 */ 7941480Smckusick u_char filler8[15]; 8041480Smckusick vu_char fold; /* fold register 0x40b3 */ 8141480Smckusick vu_int opwen; /* overlay plane write enable 0x40b4 */ 8241480Smckusick u_char filler9[3]; 8341480Smckusick vu_char tmode; /* Tile mode size 0x40bb */ 8441480Smckusick u_char filler9a[3]; 8541480Smckusick vu_char drive; /* drive register 0x40bf */ 8641480Smckusick u_char filler10[3]; 8741480Smckusick vu_char vdrive; /* vdrive register 0x40c3 */ 8841480Smckusick u_char filler10a[0x40cb-0x40c4]; 8941480Smckusick vu_char zconfig; /* Z-buffer mode 0x40cb */ 9041480Smckusick u_char filler11a[2]; 9141480Smckusick vu_short tpatt; /* Transparency pattern 0x40ce */ 9241480Smckusick u_char filler11b[3]; 9341480Smckusick vu_char dmode; /* dither mode 0x40d3 */ 9441480Smckusick u_char filler11c[3]; 9541480Smckusick vu_char en_scan; /* enable scan board to DTACK 0x40d7 */ 9641480Smckusick u_char filler11d[0x40ef-0x40d8]; 9741480Smckusick vu_char rep_rule; /* replacement rule 0x40ef */ 9841480Smckusick u_char filler12[2]; 9941480Smckusick vu_short source_x; /* source x 0x40f2 */ 10041480Smckusick u_char filler13[2]; 10141480Smckusick vu_short source_y; /* source y 0x40f6 */ 10241480Smckusick u_char filler14[2]; 10341480Smckusick vu_short dest_x; /* dest x 0x40fa */ 10441480Smckusick u_char filler15[2]; 10541480Smckusick vu_short dest_y; /* dest y 0x40fe */ 10641480Smckusick u_char filler16[2]; 10741480Smckusick vu_short wwidth; /* window width 0x4102 */ 10841480Smckusick u_char filler17[2]; 10941480Smckusick vu_short wheight; /* window height 0x4106 */ 11041480Smckusick u_char filler18[18]; 11141480Smckusick vu_short patt_x; /* pattern x 0x411a */ 11241480Smckusick u_char filler19[2]; 11341480Smckusick vu_short patt_y; /* pattern y 0x411e */ 11441480Smckusick u_char filler20[0x8012 - 0x4120]; 11541480Smckusick vu_short te_status; /* transform engine status 0x8012 */ 11641480Smckusick u_char filler21[0x1ffff-0x8014]; 11741480Smckusick }; 118