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Searched refs:writeback (Results 1 – 25 of 54) sorted by relevance

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/openbsd-src/gnu/usr.bin/binutils/include/opcode/
H A Darm.h94 unsigned writeback :1; /* == 1 means write back (base+offset) into base */ member
107 unsigned writeback :1; /* == 1 means update base after move */ member
/openbsd-src/gnu/gcc/gcc/config/arm/
H A Darm1136jfs.md47 ;; and saturation stages. The fourth stage is writeback; see below.
50 ;; MAC1 through MAC3, and a fourth writeback stage.
52 ;; The 4th-stage writeback is shared between the ALU and MAC pipelines,
54 ;; moved into the writeback stage. Because the two pipelines operate
58 ;; data cache (2), and writeback stages. (Note that this pipeline,
59 ;; including the writeback stage, is independent from the ALU & LSU pipes.)
280 ;; the difference between operations with a base register writeback.
290 ;; Load byte results are not available until the writeback stage, where
H A Dvfp.md35 ;; - A 8-stage FMAC pipeline (7 execute + writeback) with forward from
38 ;; - A 5-stage DS pipeline (4 execute + writeback) for divide/sqrt insns.
41 ;; - A 4-stage LS pipeline (execute + 2 memory + writeback) with forward from
H A Darm926ejs.md118 ;; the difference between operations with a base register writeback
H A Darm1026ejs.md155 ;; the difference between operations with a base register writeback
H A Darm1020e.md155 ;; the difference between operations with a base register writeback
/openbsd-src/usr.bin/mail/
H A Dquit.c174 writeback(rbuf); in quit()
290 writeback(rbuf); in quit()
336 writeback(FILE *res) in writeback() function
H A Dextern.h256 int writeback(FILE *);
/openbsd-src/gnu/llvm/clang/lib/CodeGen/
H A DCGCall.h305 Writeback writeback = {srcLV, temporary, toUse}; in addWriteback() local
306 Writebacks.push_back(writeback); in addWriteback()
H A DCGCall.cpp3876 const CallArgList::Writeback &writeback) { in emitWriteback() argument
3877 const LValue &srcLV = writeback.Source; in emitWriteback()
3899 llvm::Value *value = CGF.Builder.CreateLoad(writeback.Temporary); in emitWriteback()
3912 if (writeback.ToUse) { in emitWriteback()
3920 CGF.EmitARCIntrinsicUse(writeback.ToUse); in emitWriteback()
/openbsd-src/gnu/usr.bin/binutils-2.17/gas/config/
H A Dtc-arm.c284 unsigned writeback : 1; /* Operand has trailing ! */ member
3452 inst.operands[i].writeback = 1; in parse_address()
3479 inst.operands[i].writeback = 1; in parse_address()
4004 inst.operands[i].writeback = 1; in parse_operands()
4041 inst.operands[i].writeback = 1; in parse_operands()
4139 inst.operands[1].writeback = 1; in parse_operands()
4386 if (inst.operands[i].writeback) in encode_arm_addr_mode_common()
4392 assert (inst.operands[i].writeback); in encode_arm_addr_mode_common()
4489 assert (!inst.operands[i].writeback); in encode_arm_cp_address()
4503 if (inst.operands[i].writeback) in encode_arm_cp_address()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td66 // consumes the pipe for one cycle at issue and another cycle at writeback.
95 // but only consume the pipe for one cycle at issue and a cycle at writeback.
208 // The ID pipe is consumed for 2 cycles: issue and writeback.
215 // The ID pipe is consumed for 2 cycles: issue and writeback.
633 // Only the first WriteVLD and WriteAdr for writeback matches def operands.
774 // Only the WriteAdr for writeback matches a def operands.
/openbsd-src/gnu/usr.bin/binutils-2.17/opcodes/
H A Darm-dis.c2499 bfd_boolean writeback = FALSE, postind = FALSE; in print_insn_thumb32() local
2529 writeback = TRUE; in print_insn_thumb32()
2534 writeback = TRUE; in print_insn_thumb32()
2558 func (stream, writeback ? "]!" : "]"); in print_insn_thumb32()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2097 bool writeback = (P == 0) || (W == 1); in DecodeAddrMode2IdxInstruction() local
2099 if (P && writeback) in DecodeAddrMode2IdxInstruction()
2101 else if (!P && writeback) in DecodeAddrMode2IdxInstruction()
2104 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
2218 bool writeback = (W == 1) | (P == 0); in DecodeAddrMode3Instruction() local
2240 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2254 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
2271 if (!type && writeback && Rn == 15) in DecodeAddrMode3Instruction()
2273 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2288 if (!type && writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
[all …]
/openbsd-src/gnu/usr.bin/binutils-2.17/cpu/
H A Dm32r.cpu229 (pipeline p-non-mem "" () ((fetch) (decode) (execute) (writeback)))
230 (pipeline p-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
287 (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
300 (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
301 (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
302 (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
353 (pipeline p-o "" () ((fetch) (decode) (execute) (writeback)))
354 (pipeline p-s "" () ((fetch) (decode) (execute) (writeback)))
355 (pipeline p-o-mem "" () ((fetch) (decode) (execute) (memory) (writeback)))
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMScheduleM7.td30 // EX3: slow load data integer writeback FP operation
31 // EX4: store data FP writeback
H A DARMScheduleA9.td447 // register file writeback!).
2336 // A9WriteAdr consumes AGU regardless address writeback. But it's
2346 // Store either has no def operands, or the one def for address writeback.
2364 // Load multiple with address writeback has an extra def operand in
2368 // resources are identical, For stores only the address writeback
2383 // Note: Unlike VLDM, VLD1 expects the writeback operand after the
2404 // address writeback.
H A DARMScheduleA57.td591 // TODO: no writeback latency defined in documentation (implemented as 1 cyc)
625 // Store, immed pre-indexed (1cyc "S, I0/I1", 1cyc writeback)
687 // TODO: no writeback latency defined in documentation
1262 // 1-2 reg: 5cyc L, +I for writeback, 1 cyc wb latency
1267 // 3-4 reg: 6cyc L, +I for writeback, 1 cyc wb latency
H A DARMInstrNEON.td626 // ...with address register writeback:
826 // ...with address register writeback:
899 // ...with address register writeback:
959 // ...with address register writeback:
1115 // ...with address register writeback:
1178 // ...with address register writeback:
1249 // ...with address register writeback:
1327 // ...with address register writeback:
1419 // ...with address register writeback:
1501 // ...with address register writeback:
[all …]
H A DARMInstrMVE.td5968 class MVE_vldst24_base<bit writeback, bit fourregs, bits<2> stage, bits<2> size,
5977 let Inst{21} = writeback;
5993 // A parameter class used to encapsulate all the ways the writeback
5994 // variants of VLD20 and friends differ from the non-writeback ones.
5997 bit writeback = b;
6028 : MVE_vldst24_base<wb.writeback, n.bit0, pat, size, 1,
6037 : MVE_vldst24_base<wb.writeback, n.bit0, pat, size, 0,
6045 // vector lane; writeback or no writeback.
6234 // generate three writeback modes (none, preindex, postindex).
6294 // names shown in the defm, with _pre or _post appended for writeback,
[all …]
/openbsd-src/sys/net/
H A Dpf_norm.c1273 struct pf_state_peer *dst, int *writeback) in pf_normalize_tcp_stateful() argument
1374 *writeback = 1; in pf_normalize_tcp_stateful()
/openbsd-src/gnu/llvm/clang/docs/
H A DAutomaticReferenceCounting.rst957 * the conversion is a well-formed :ref:`pass-by-writeback
1040 Passing to an out parameter by writeback
1045 candidate for :arc-term:`pass-by-writeback`` if:
1051 a pass-by-writeback is always worse than an implicit conversion sequence not
1052 requiring a pass-by-writeback.
1054 The pass-by-writeback is ill-formed if the argument expression does not have a
1071 below, where their store to the writeback temporary is not immediately seen
1074 A pass-by-writeback is evaluated as follows:
1078 and no further work is required for the pass-by-writeback.
1417 caution in the following rules about writeback.
/openbsd-src/gnu/llvm/llvm/docs/
H A DAMDGPUUsage.rst6496 Subsequent access from the GPU will automatically invalidate or writeback
6499 invalidation or writeback is required for coherence.
6501 different agents a ``buffer_wbl2`` is required. It will writeback dirty L2
7412 - Performs L2 writeback to
7456 writeback have
7554 - Performs L2 writeback to
7596 writeback have
7742 - Performs L2 writeback to
8042 - Performs L2 writeback to
8083 to global and L2 writeback
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1583 unsigned writeback = fieldFromInstruction(insn, 11, 1); in DecodeAuthLoadInstruction() local
1602 if (writeback && Rt == Rn && Rn != 31) { in DecodeAuthLoadInstruction()
/openbsd-src/gnu/usr.bin/binutils-2.17/opcodes/po/
H A Dnl.po75 msgid "address writeback not allowed"
76 msgstr "address writeback niet toegestaan"

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