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Searched refs:setcc (Results 1 – 25 of 56) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td289 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), bb:$imm16),
292 def : Pat<(brcond (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), bb:$imm16),
296 def : Pat<(i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)),
299 def : Pat<(i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)),
303 def : Pat<(select (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), FPR32Op:$rx, FPR32Op:$false),
311 def : Pat<(select (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), FPR64Op:$rx, FPR64Op:$false),
322 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), bb:$imm16),
325 def : Pat<(brcond (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), bb:$imm16),
329 def : Pat<(i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)),
332 def : Pat<(i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)),
[all …]
H A DCSKYInstrInfoF1.td303 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), bb:$imm16),
306 def : Pat<(brcond (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), bb:$imm16),
310 def : Pat<(i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)),
313 def : Pat<(i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)),
319 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), bb:$imm16),
322 def : Pat<(brcond (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), bb:$imm16),
326 def : Pat<(i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)),
329 def : Pat<(i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)),
354 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)), bb:$imm16),
356 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)),
[all …]
/openbsd-src/gnu/usr.bin/perl/ext/POSIX/t/
H A Dtermios.t150 $t->setcc($i, 0);
157 $t->setcc($i, ++$c);
163 $t->setcc($i, ++$c);
/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td38 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))],
42 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))],
90 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
93 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))],
H A DWebAssemblyInstrFloat.td38 [(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))],
42 [(set I32:$dst, (setcc F64:$lhs, F64:$rhs, cond))],
/openbsd-src/gnu/gcc/gcc/
H A Dgcse.c2773 cprop_jump (basic_block bb, rtx setcc, rtx jump, rtx from, rtx src) in cprop_jump() argument
2792 if (setcc != NULL_RTX in cprop_jump()
2793 && !modified_between_p (from, setcc, jump) in cprop_jump()
2794 && !modified_between_p (src, setcc, jump)) in cprop_jump()
2797 rtx setcc_set = single_set (setcc); in cprop_jump()
2798 rtx setcc_note = find_reg_equal_equiv_note (setcc); in cprop_jump()
2805 setcc = NULL_RTX; in cprop_jump()
2820 if (setcc && modified_in_p (new, setcc)) in cprop_jump()
2851 if (setcc != NULL && CC0_P (SET_DEST (single_set (setcc)))) in cprop_jump()
2852 delete_insn (setcc); in cprop_jump()
[all …]
/openbsd-src/gnu/llvm/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td188 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
603 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
1363 // setcc convenience fragments.
1365 (setcc node:$lhs, node:$rhs, SETOEQ)>;
1367 (setcc node:$lhs, node:$rhs, SETOGT)>;
1369 (setcc node:$lhs, node:$rhs, SETOGE)>;
1371 (setcc node:$lhs, node:$rhs, SETOLT)>;
1373 (setcc node:$lhs, node:$rhs, SETOLE)>;
1375 (setcc node:$lhs, node:$rhs, SETONE)>;
1377 (setcc node:$lhs, node:$rhs, SETO)>;
[all …]
/openbsd-src/gnu/usr.bin/gcc/gcc/
H A Dgcse.c4059 cprop_jump (bb, setcc, jump, from, src) in cprop_jump() argument
4061 rtx setcc;
4072 if (setcc != NULL_RTX
4073 && !modified_between_p (from, setcc, jump)
4074 && !modified_between_p (src, setcc, jump))
4076 rtx setcc_set = single_set (setcc);
4082 setcc = NULL_RTX;
4098 if (setcc
4099 && modified_in_p (new, setcc))
4113 if (setcc != NULL && CC0_P (SET_DEST (single_set (setcc))))
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.td3359 // match setcc on i1 variables.
3377 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)),
3379 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3398 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)),
3400 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
3403 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)),
3417 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)),
3419 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3433 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
3435 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
[all …]
H A DPPCInstrP10.td1949 defm : IntSetP10RevSetBool<setcc, i32, immZExt16, imm32SExt16,
1951 defm : P10ReverseSetBool<(i1 (setcc i32:$s1, imm:$imm, SETNE)),
1956 defm : IntSetP10RevSetBool<setcc, i64, immZExt16, imm64SExt16,
1958 defm : P10ReverseSetBool<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)),
1965 defm : FSetP10RevSetBool<setcc, f32, FCMPUS>;
1966 defm : FSetP10RevSetBool<setcc, f64, FCMPUD>;
1967 defm : FSetP10RevSetBool<setcc, f128, XSCMPUQP>;
/openbsd-src/gnu/gcc/gcc/config/i386/
H A Dk6.md133 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc")
139 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc")
145 (and (eq_attr "type" "alu,alu1,negnot,icmp,test,imovx,incdec,setcc")
H A Dppro.md740 …(eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseim…
748 …(eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseim…
754 …(eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseim…
762 …(eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseim…
/openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td41 // and setcc instructions
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td177 def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
189 def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs2),
204 def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
219 def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
222 def : Pat<(vti.Mask (setcc (vti.Vector (SplatPatKind xop_kind:$rs2)),
240 def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
252 def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1),
257 def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1),
263 def : Pat<(fvti.Mask (setcc (SplatFPOp fvti.ScalarRegClass:$rs2),
/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td187 def : Pat<(brcond (xor (GRLenVT (setcc RegTy:$fj, RegTy:$fk, cc)), -1),
190 def : Pat<(brcond (GRLenVT (setcc RegTy:$fj, RegTy:$fk, cc)), bb:$imm21),
232 : Pat<(select (GRLenVT (setcc RegTy:$a, RegTy:$b, cc)), RegTy:$t, RegTy:$f),
/openbsd-src/gnu/llvm/llvm/include/llvm/Target/GlobalISel/
H A DSelectionDAGCompat.td39 // SelectionDAG has one setcc for all compares. This differentiates
175 def : GINodeEquiv<G_ICMP, setcc> {
/openbsd-src/gnu/usr.bin/gcc/gcc/config/i386/
H A Dk6.md57 … (eq_attr "type" "ishift,ishift1,rotate,rotate1,alu1,negnot,alu,icmp,test,imovx,incdec,setcc,lea"))
H A Dathlon.md66 …,imov,imovx,lea,incdec,ishift,ishift1,rotate,rotate1,ibr,call,callv,icmov,cld,pop,setcc,push,pop"))
/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVVPInstrInfo.td198 // setcc (lhs, rhs, cc, mask, vl)
H A DVEInstrInfo.td2038 def : Pat<(i32 (setcc i32:$l, i32:$r, CCSIOp:$cond)),
2040 def : Pat<(i32 (setcc i32:$l, i32:$r, CCUIOp:$cond)),
2042 def : Pat<(i32 (setcc i64:$l, i64:$r, CCSIOp:$cond)),
2044 def : Pat<(i32 (setcc i64:$l, i64:$r, CCUIOp:$cond)),
2046 def : Pat<(i32 (setcc f32:$l, f32:$r, cond:$cond)),
2048 def : Pat<(i32 (setcc f64:$l, f64:$r, cond:$cond)),
2050 def : Pat<(i32 (setcc f128:$l, f128:$r, cond:$cond)),
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMips16InstrInfo.td1399 // setcc patterns
1426 // setcc instead and earlier I had implemented setcc first so may have masked
1427 // the problem. The setcc variants are suboptimal for mips16 so I may wantto
1429 // combinations of brcond and setcc.
H A DMips64r6InstrInfo.td259 // FIXME: Ideally, setcc would always produce an i64 on MIPS64 targets.
/openbsd-src/gnu/gcc/gcc/config/m32c/
H A Dcond.md23 ; conditionals - cmp, jcc, setcc, etc.
/openbsd-src/gnu/llvm/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td1212 /// setcc patterns, only matched when none of the above brcond
1216 // setcc 2 register operands
1243 // setcc reg/imm operands
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td191 def AMDGPUSetCCOp : SDTypeProfile<1, 3, [ // setcc

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