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/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVCallingConv.td17 : CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27))>;
21 F8_F, F9_F, (sequence "F%u_F", 18, 27))>;
25 F8_D, F9_D, (sequence "F%u_D", 18, 27))>;
33 (sequence "X%u", 3, 9),
34 (sequence "X%u", 10, 11),
35 (sequence "X%u", 12, 17),
36 (sequence "X%u", 18, 27),
37 (sequence "X%u", 28, 31))>;
41 (sequence "X%u", 3, 9),
42 (sequence "X%u", 10, 11),
[all …]
H A DRISCVRegisterInfo.td125 // The order of registers represents the preferred allocation sequence.
128 (sequence "X%u", 10, 17),
129 (sequence "X%u", 5, 7),
130 (sequence "X%u", 28, 31),
131 (sequence "X%u", 8, 9),
132 (sequence "X%u", 18, 27),
133 (sequence "X%u", 0, 4)
154 def GPRJALR : RegisterClass<"RISCV", [XLenVT], 32, (sub GPR, (sequence "X%u", 0, 5))> {
159 (sequence "X%u", 10, 15),
160 (sequence "X%u", 8, 9)
[all …]
/openbsd-src/gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/compile/
H A D920625-1.c40 insn_t *sequence, in recurse() argument
64 sequence[n_insns] = insn; in recurse()
66 synth(sequence, n_insns + 1, values, n_values, in recurse()
77 sequence[n_insns] = insn; in recurse()
78 test_sequence(sequence, n_insns + 1); in recurse()
82 synth(insn_t *sequence, in synth() argument
97 last_dest = sequence[n_insns - 1].d; in synth()
115 …recurse(ADD_CIO, n_values, s1, s2, v, 1, sequence, n_insns, values, n_values + 1, goal_value, al… in synth()
117 …recurse(ADD_CI, n_values, s1, s2, v, 1, sequence, n_insns, values, n_values + 1, goal_value, all… in synth()
120 …recurse(SUB_CIO, n_values, s1, s2, v, 1, sequence, n_insns, values, n_values + 1, goal_value, al… in synth()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/
H A DCSKYCallingConv.td13 def CSR_I32 : CalleeSavedRegs<(add R8, R15, (sequence "R%u", 4, 7),
14 (sequence "R%u", 9, 11), (sequence "R%u", 16, 17), R28)>;
15 def CSR_GPR_FPR32 : CalleeSavedRegs<(add CSR_I32, (sequence "F%u_32", 8, 15))>;
17 (sequence "F%u_64", 8, 15))>;
22 (sequence "R%u", 0, 3),
23 (sequence "R%u", 4, 7),
24 (sequence "R%u", 9, 13),
25 (sequence "R%u", 16, 31))>;
28 (sequence "F%u_32", 0, 15))>;
30 (sequence "F%u_64", 0, 15))>;
[all …]
H A DCSKYRegisterInfo.td94 [(add (sequence "R%u", 0, 31)), (add (sequence "R%u", 1, 32))],
150 // The order of registers represents the preferred allocation sequence.
153 (add (sequence "R%u", 0, 3), (sequence "R%u", 12, 13),
154 (sequence "R%u", 18, 25), R15, (sequence "R%u", 4, 11),
155 (sequence "R%u", 16, 17), (sequence "R%u", 26, 27), R28,
156 (sequence "R%u", 29, 30), R14, R31)> {
163 (add (sequence "R%u", 0, 3), (sequence "R%u", 12, 13), R15,
164 (sequence "R%u", 4, 11), R14)> {
171 (add (sequence "R%u", 0, 7))> {
189 // The order of registers represents the preferred allocation sequence.
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.td59 def Int1Regs : NVPTXRegClass<[i1], 8, (add (sequence "P%u", 0, 4))>;
60 def Int16Regs : NVPTXRegClass<[i16], 16, (add (sequence "RS%u", 0, 4))>;
61 def Int32Regs : NVPTXRegClass<[i32], 32, (add (sequence "R%u", 0, 4), VRFrame32, VRFrameLocal32)>;
62 def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%u", 0, 4), VRFrame64, VRFrameLocal64)>;
63 def Float16Regs : NVPTXRegClass<[f16,bf16], 16, (add (sequence "H%u", 0, 4))>;
64 def Float16x2Regs : NVPTXRegClass<[v2f16,v2bf16], 32, (add (sequence "HH%u", 0, 4))>;
65 def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%u", 0, 4))>;
66 def Float64Regs : NVPTXRegClass<[f64], 64, (add (sequence "FL%u", 0, 4))>;
67 def Int32ArgRegs : NVPTXRegClass<[i32], 32, (add (sequence "ia%u", 0, 4))>;
68 def Int64ArgRegs : NVPTXRegClass<[i64], 64, (add (sequence "la%u", 0, 4))>;
[all …]
/openbsd-src/sys/dev/pci/drm/include/linux/
H A Dseqlock.h15 unsigned int sequence; member
22 s->sequence = 0; in __seqcount_init()
36 r = s->sequence; in __read_seqcount_begin()
55 return (s->sequence != start); in __read_seqcount_retry()
68 s->sequence++; in write_seqcount_begin()
76 s->sequence++; in write_seqcount_end()
82 unsigned int r = s->sequence; in raw_read_seqcount()
161 return READ_ONCE(sm->seq.sequence); in seqprop_sequence()
/openbsd-src/gnu/llvm/lldb/source/Symbol/
H A DLineTable.cpp29 for (const auto &sequence : sequences) { in LineTable() local
30 LineSequenceImpl *seq = static_cast<LineSequenceImpl *>(sequence.get()); in LineTable()
70 LineSequence *sequence, lldb::addr_t file_addr, uint32_t line, in AppendLineEntryToSequence() argument
74 assert(sequence != nullptr); in AppendLineEntryToSequence()
75 LineSequenceImpl *seq = reinterpret_cast<LineSequenceImpl *>(sequence); in AppendLineEntryToSequence()
105 void LineTable::InsertSequence(LineSequence *sequence) { in InsertSequence() argument
106 assert(sequence != nullptr); in InsertSequence()
107 LineSequenceImpl *seq = reinterpret_cast<LineSequenceImpl *>(sequence); in InsertSequence()
408 LineSequenceImpl sequence; in LinkLineTable() local
451 if (!sequence.m_entries.empty() && in LinkLineTable()
[all …]
/openbsd-src/gnu/llvm/llvm/bindings/python/llvm/tests/
H A Dtest_disassembler.py12 sequence = '\x67\xe3\x81' # jcxz -127
17 count, s = disassembler.get_instruction(sequence)
26 sequence = '\x67\xe3\x81\x01\xc7' # jcxz -127; addl %eax, %edi
30 instructions = list(disassembler.get_instructions(sequence))
37 sequence = '\x10\x40\x2d\xe9'
42 count, s = disassembler.get_instruction(sequence)
/openbsd-src/regress/usr.bin/mandoc/roff/mc/
H A Dargs.out_lint3 mandoc: args.in:11:5: ERROR: skipping unusable escape sequence: mc \CXX
4 mandoc: args.in:13:5: UNSUPP: unsupported escape sequence: \!
5 mandoc: args.in:13:5: ERROR: skipping unusable escape sequence: mc \!
6 mandoc: args.in:15:5: ERROR: skipping unusable escape sequence: mc \a
7 mandoc: args.in:21:5: ERROR: skipping unusable escape sequence: mc \fR
9 mandoc: args.in:27:5: ERROR: skipping unusable escape sequence: mc \o'o/'
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td99 (add (sequence "R%uL", 0, 5),
100 (sequence "R%uL", 15, 6)),
101 [(add (sequence "R%uL", 0, 15))]>;
103 (add (sequence "R%uH", 0, 5),
104 (sequence "R%uH", 15, 6)),
105 [(add (sequence "R%uH", 0, 15))]>;
107 (add (sequence "R%uD", 0, 5),
108 (sequence "R%uD", 15, 6)),
109 [(add (sequence "R%uD", 0, 15))]>;
115 (add (sequence "R%uL", 0, 5),
[all …]
/openbsd-src/regress/usr.bin/mandoc/roff/esc/
H A DO1.out_lint1 mandoc: O1.in:11:6: WARNING: invalid escape sequence argument: \O5
2 mandoc: O1.in:12:7: WARNING: invalid escape sequence argument: \O(52
3 mandoc: O1.in:13:7: UNSUPP: unsupported escape sequence: \O[5dummy]
4 mandoc: O1.in:14:6: WARNING: invalid escape sequence argument: \O6
5 mandoc: O1.in:15:6: UNSUPP: unsupported escape sequence: \O0
H A Do.out_lint1 mandoc: o.in:21:20: UNSUPP: unsupported escape sequence: \r
2 mandoc: o.in:21:24: UNSUPP: unsupported escape sequence: \r
4 mandoc: o.in:55:15: ERROR: incomplete escape sequence: \o'xy
H A Dunsupp.out_lint1 mandoc: unsupp.in:7:20: UNSUPP: unsupported escape sequence: \!
3 mandoc: unsupp.in:8:17: UNSUPP: unsupported escape sequence: \?
4 mandoc: unsupp.in:8:21: UNSUPP: unsupported escape sequence: \?
/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DVERegisterInfo.td79 (sequence "PMCR%u", 0, 3),
80 (sequence "PMC%u", 0, 14))>;
174 (add (sequence "SW%u", 0, 7),
175 (sequence "SW%u", 34, 63),
176 (sequence "SW%u", 8, 33))>;
178 (add (sequence "SX%u", 0, 7),
179 (sequence "SX%u", 34, 63),
180 (sequence "SX%u", 8, 33))>;
182 (add (sequence "SF%u", 0, 7),
183 (sequence "SF%u", 34, 63),
[all …]
/openbsd-src/gnu/usr.bin/perl/cpan/Encode/t/
H A Dutf8warnings.t20 …'UTF-8', "\xed\xa0\x80", FB_CROAK | LEAVE_SRC) }, 'Surrogate UTF-8 byte sequence \xED\xA0\x80 is d…
21 …ipt line /, 'Error message contains strict UTF-8 name and original (not decoded) invalid sequence';
24 is_deeply \@invalid, [ 0xED, 0xA0, 0x80 ], 'Fallback coderef contains invalid byte sequence 0xED, 0…
26 ok ! defined eval { decode('UTF-8', "\xed\xa0", FB_CROAK | LEAVE_SRC) }, 'Invalid byte sequence \xE…
27 …ipt line /, 'Error message contains strict UTF-8 name and original (not decoded) invalid sequence';
30 is_deeply \@invalid, [ 0xED, 0xA0 ], 'Fallback coderef contains invalid byte sequence 0xED, 0xA0';
32 ok ! defined eval { decode('utf8', "\xed\xa0", FB_CROAK | LEAVE_SRC) }, 'Invalid byte sequence \xED…
33 … line /, 'Error message contains non-strict utf8 name and original (not decoded) invalid sequence';
35 is_deeply \@invalid, [ 0xED, 0xA0 ], 'Fallback coderef contains invalid byte sequence 0xED, 0xA0';
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td135 (add (sequence "VGPR%u", 40, 47),
136 (sequence "VGPR%u", 56, 63),
137 (sequence "VGPR%u", 72, 79),
138 (sequence "VGPR%u", 88, 95),
139 (sequence "VGPR%u", 104, 111),
140 (sequence "VGPR%u", 120, 127),
141 (sequence "VGPR%u", 136, 143),
142 (sequence "VGPR%u", 152, 159),
143 (sequence "VGPR%u", 168, 175),
144 (sequence "VGPR%u", 184, 191),
[all …]
H A DR600RegisterInfo.td153 (add (sequence "ArrayBase%u", 448, 480))> {
165 def R600_Addr : RegisterClass <"AMDGPU", [i32], 32, (add (sequence "Addr%u_X", 0, 127))>;
178 (add (sequence "KC0_%u_X", 128, 159))>;
181 (add (sequence "KC0_%u_Y", 128, 159))>;
184 (add (sequence "KC0_%u_Z", 128, 159))>;
187 (add (sequence "KC0_%u_W", 128, 159))>;
194 (add (sequence "KC1_%u_X", 160, 191))>;
197 (add (sequence "KC1_%u_Y", 160, 191))>;
200 (add (sequence "KC1_%u_Z", 160, 191))>;
203 (add (sequence "KC1_%u_W", 160, 191))>;
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsCallingConv.td362 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
363 (sequence "S%u", 7, 0))>;
365 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
366 (sequence "S%u", 7, 0))> {
367 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2));
370 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
371 (sequence "S%u", 7, 0))>;
374 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
375 (sequence "S%u", 7, 0))>;
379 (sequence "S%u_64", 7, 0))>;
[all …]
/openbsd-src/gnu/usr.bin/perl/cpan/CPAN/lib/CPAN/Kwalify/
H A Ddistroprefs.dd37 "sequence" => [
50 "sequence" => [
73 "sequence" => [
95 "sequence" => [
130 "sequence" => [
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCCallingConv.td322 def CSR_SVR32_ColdCC_Common : CalleeSavedRegs<(add (sequence "R%u", 4, 10),
323 (sequence "R%u", 14, 31),
324 (sequence "CR%u", 0, 7))>;
327 F0, (sequence "F%u", 2, 31))>;
331 (sequence "V%u", 0, 1),
332 (sequence "V%u", 3, 31))>;
335 (sequence "S%u", 4, 10),
336 (sequence "S%u", 14, 31))>;
338 def CSR_SVR64_ColdCC : CalleeSavedRegs<(add (sequence "X%u", 4, 10),
339 (sequence "X%u", 14, 31),
[all …]
/openbsd-src/gnu/llvm/llvm/include/llvm/ADT/
H A DPriorityQueue.h31 const Sequence &sequence = Sequence())
32 : std::priority_queue<T, Sequence, Compare>(compare, sequence)
38 const Sequence &sequence = Sequence())
39 : std::priority_queue<T, Sequence, Compare>(begin, end, compare, sequence)
/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td84 // The order of registers represents the preferred allocation sequence.
88 (sequence "R%u", 4, 11),
90 (sequence "R%u", 12, 20),
92 (sequence "R%u", 22, 31),
94 (sequence "R%u", 0, 3),
106 (sequence "R%u", 4, 20)
153 // The order of registers represents the preferred allocation sequence.
154 def FPR32 : RegisterClass<"LoongArch", [f32], 32, (sequence "F%u", 0, 31)>;
155 def FPR64 : RegisterClass<"LoongArch", [f64], 64, (sequence "F%u_64", 0, 31)>;
162 def CFR : RegisterClass<"LoongArch", [GRLenVT], 32, (sequence "FCC%u", 0, 7)> {
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.td89 def DR8 : MxRegClass<[i8], 16, (sequence "BD%u", 0, 7)>;
90 def DR16 : MxRegClass<[i16], 16, (sequence "WD%u", 0, 7)>;
91 def DR32 : MxRegClass<[i32], 32, (sequence "D%u", 0, 7)>;
94 def AR16 : MxRegClass<[i16], 16, (add (sequence "WA%u", 0, 6), WSP)>;
95 def AR32 : MxRegClass<[i32], 32, (add (sequence "A%u", 0, 6), SP)>;
97 def AR32_NOSP : MxRegClass<[i32], 32, (sequence "A%u", 0, 6)>;
127 def SPILL_R : MxRegClass<[i32], 32, (add SP, (sequence "A%u", 6, 0), (sequence "D%u", 7, 0))>;
/openbsd-src/gnu/usr.bin/gcc/gcc/testsuite/gcc.c-torture/unsorted/
H A Dconsec.c8 sequence (a, b, c, d);
9 sequence (d, c, b, a);
14 sequence (111, 0, 0, 222, 0, 333);

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