Home
last modified time | relevance | path

Searched refs:reg_data (Results 1 – 25 of 41) sorted by relevance

12

/openbsd-src/sys/dev/pci/drm/amd/amdgpu/
H A Dnbio_v2_3.c501 uint32_t reg_data = 0; in nbio_v2_3_apply_lc_spc_mode_wa() local
508 reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL); in nbio_v2_3_apply_lc_spc_mode_wa()
509 link_width = (reg_data & PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK) in nbio_v2_3_apply_lc_spc_mode_wa()
517 reg_data = RREG32_PCIE(smnPCIE_LC_CNTL6); in nbio_v2_3_apply_lc_spc_mode_wa()
518 reg_data &= ~PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK; in nbio_v2_3_apply_lc_spc_mode_wa()
519 reg_data |= (0x2 << PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT); in nbio_v2_3_apply_lc_spc_mode_wa()
520 WREG32_PCIE(smnPCIE_LC_CNTL6, reg_data); in nbio_v2_3_apply_lc_spc_mode_wa()
526 uint32_t reg_data = 0; in nbio_v2_3_apply_l1_link_width_reconfig_wa() local
531 reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL); in nbio_v2_3_apply_l1_link_width_reconfig_wa()
532 reg_data |= PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK; in nbio_v2_3_apply_l1_link_width_reconfig_wa()
[all …]
H A Dvcn_v1_0.c650 uint32_t reg_data = 0; in vcn_v1_0_clock_gating_dpg_mode() local
654 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
656 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
657 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
658 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
659 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
665 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
667 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
668 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
669 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; in vcn_v1_0_clock_gating_dpg_mode()
[all …]
H A Dimu_v11_0.c351 u32 reg_data; in imu_v11_0_program_rlc_ram() local
373 reg_data = RREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX); in imu_v11_0_program_rlc_ram()
374 reg_data |= GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK; in imu_v11_0_program_rlc_ram()
375 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, reg_data); in imu_v11_0_program_rlc_ram()
H A Dvcn_v2_0.c598 uint32_t reg_data = 0; in vcn_v2_0_clock_gating_dpg_mode() local
602 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_clock_gating_dpg_mode()
604 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_0_clock_gating_dpg_mode()
605 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v2_0_clock_gating_dpg_mode()
606 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; in vcn_v2_0_clock_gating_dpg_mode()
607 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | in vcn_v2_0_clock_gating_dpg_mode()
628 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
1205 uint32_t reg_data = 0; in vcn_v2_0_pause_dpg_mode() local
1212 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & in vcn_v2_0_pause_dpg_mode()
1222 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; in vcn_v2_0_pause_dpg_mode()
[all …]
H A Dvcn_v2_5.c685 uint32_t reg_data = 0; in vcn_v2_5_clock_gating_dpg_mode() local
689 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_clock_gating_dpg_mode()
691 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v2_5_clock_gating_dpg_mode()
692 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v2_5_clock_gating_dpg_mode()
693 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; in vcn_v2_5_clock_gating_dpg_mode()
694 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | in vcn_v2_5_clock_gating_dpg_mode()
715 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
1452 uint32_t reg_data = 0; in vcn_v2_5_pause_dpg_mode() local
1459 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & in vcn_v2_5_pause_dpg_mode()
1470 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; in vcn_v2_5_pause_dpg_mode()
[all …]
H A Dvcn_v4_0.c778 uint32_t reg_data = 0; in vcn_v4_0_disable_clock_gating_dpg_mode() local
784 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v4_0_disable_clock_gating_dpg_mode()
785 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v4_0_disable_clock_gating_dpg_mode()
786 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; in vcn_v4_0_disable_clock_gating_dpg_mode()
787 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | in vcn_v4_0_disable_clock_gating_dpg_mode()
807 VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v4_0_disable_clock_gating_dpg_mode()
1546 uint32_t reg_data = 0; in vcn_v4_0_pause_dpg_mode() local
1553 reg_data = RREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE) & in vcn_v4_0_pause_dpg_mode()
1562 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; in vcn_v4_0_pause_dpg_mode()
1563 WREG32_SOC15(VCN, inst_idx, regUVD_DPG_PAUSE, reg_data); in vcn_v4_0_pause_dpg_mode()
[all …]
H A Damdgpu_amdkfd_gfx_v10.h58 uint32_t *reg_data);
H A Dvcn_v3_0.c829 uint32_t reg_data = 0; in vcn_v3_0_clock_gating_dpg_mode() local
833 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_clock_gating_dpg_mode()
835 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v3_0_clock_gating_dpg_mode()
836 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v3_0_clock_gating_dpg_mode()
837 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; in vcn_v3_0_clock_gating_dpg_mode()
838 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | in vcn_v3_0_clock_gating_dpg_mode()
859 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
1602 uint32_t reg_data = 0; in vcn_v3_0_pause_dpg_mode() local
1609 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & in vcn_v3_0_pause_dpg_mode()
1618 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; in vcn_v3_0_pause_dpg_mode()
[all …]
H A Dpsp_v13_0.c739 uint32_t reg_data; in psp_v13_0_fatal_error_recovery_quirk() local
743 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67); in psp_v13_0_fatal_error_recovery_quirk()
744 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10); in psp_v13_0_fatal_error_recovery_quirk()
H A Damdgpu_atombios.c1444 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = in amdgpu_atombios_init_mc_reg_table() local
1465 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && in amdgpu_atombios_init_mc_reg_table()
1467 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) in amdgpu_atombios_init_mc_reg_table()
1471 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) in amdgpu_atombios_init_mc_reg_table()
1476 (u32)le32_to_cpu(*((u32 *)reg_data + j)); in amdgpu_atombios_init_mc_reg_table()
1487 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) in amdgpu_atombios_init_mc_reg_table()
1488 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); in amdgpu_atombios_init_mc_reg_table()
1490 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) in amdgpu_atombios_init_mc_reg_table()
H A Damdgpu_amdkfd_gfx_v10.c983 uint32_t *reg_data) in kgd_gfx_v10_build_grace_period_packet_info() argument
985 *reg_data = wait_times; in kgd_gfx_v10_build_grace_period_packet_info()
994 *reg_data = REG_SET_FIELD(*reg_data, in kgd_gfx_v10_build_grace_period_packet_info()
H A Damdgpu_amdkfd_gfx_v9.h103 uint32_t *reg_data);
H A Dvcn_v4_0_3.c630 uint32_t reg_data = 0; in vcn_v4_0_3_disable_clock_gating_dpg_mode()
636 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; in vcn_v4_0_3_disable_clock_gating_dpg_mode()
637 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; in vcn_v4_0_3_disable_clock_gating_dpg_mode()
638 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; in vcn_v4_0_3_disable_clock_gating_dpg_mode()
639 reg_data &= ~(UVD_CGC_CTRL__SYS_MODE_MASK | in vcn_v4_0_3_disable_clock_gating_dpg_mode()
653 VCN, 0, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);
616 uint32_t reg_data = 0; vcn_v4_0_3_disable_clock_gating_dpg_mode() local
/openbsd-src/gnu/usr.bin/gcc/gcc/
H A Dregclass.c2181 struct reg_info_data *reg_data; local
2222 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2223 reg_data->min_index = old_allocated;
2224 reg_data->max_index = regno_allocated - 1;
2225 reg_data->next = reg_info_head;
2226 reg_info_head = reg_data;
2234 for (reg_data = reg_info_head;
2235 reg_data && reg_data->max_index >= min;
2236 reg_data = reg_data->next)
2238 size_t min_index = reg_data->min_index;
[all …]
/openbsd-src/gnu/gcc/gcc/
H A Dregclass.c2168 struct reg_info_data *reg_data; in allocate_reg_info() local
2221 reg_data = xcalloc (size_info, 1); in allocate_reg_info()
2222 reg_data->min_index = old_allocated; in allocate_reg_info()
2223 reg_data->max_index = regno_allocated - 1; in allocate_reg_info()
2224 reg_data->next = reg_info_head; in allocate_reg_info()
2225 reg_info_head = reg_data; in allocate_reg_info()
2233 for (reg_data = reg_info_head; in allocate_reg_info()
2234 reg_data && reg_data->max_index >= min; in allocate_reg_info()
2235 reg_data = reg_data->next) in allocate_reg_info()
2237 size_t min_index = reg_data->min_index; in allocate_reg_info()
[all …]
/openbsd-src/gnu/llvm/lldb/source/Plugins/Process/scripted/
H A DScriptedThread.cpp124 std::optional<std::string> reg_data = GetInterface()->GetRegisterContext(); in CreateRegisterContextForFrame() local
125 if (!reg_data) in CreateRegisterContextForFrame()
131 std::make_shared<DataBufferHeap>(reg_data->c_str(), reg_data->size())); in CreateRegisterContextForFrame()
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dce110/
H A Ddce110_compressor.c245 uint32_t reg_data; in dce110_compressor_disable_fbc() local
247 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); in dce110_compressor_disable_fbc()
248 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN); in dce110_compressor_disable_fbc()
249 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data); in dce110_compressor_disable_fbc()
H A Ddce110_transform_v.c633 uint32_t reg_data = 0; in dce110_xfmv_set_pixel_storage_depth() local
658 reg_data, in dce110_xfmv_set_pixel_storage_depth()
664 reg_data, in dce110_xfmv_set_pixel_storage_depth()
669 dm_write_reg(xfm->ctx, mmLBV_DATA_FORMAT, reg_data); in dce110_xfmv_set_pixel_storage_depth()
/openbsd-src/sys/dev/pci/
H A Dif_em_hw.c1572 uint32_t reg_data; in em_init_hw() local
1580 reg_data = E1000_READ_REG(hw, STATUS); in em_init_hw()
1581 reg_data &= ~0x80000000; in em_init_hw()
1582 E1000_WRITE_REG(hw, STATUS, reg_data); in em_init_hw()
1749 (uint16_t *)&reg_data); in em_init_hw()
1775 reg_data = E1000_READ_REG(hw, TCTL); in em_init_hw()
1776 reg_data |= E1000_TCTL_RTLC; in em_init_hw()
1777 E1000_WRITE_REG(hw, TCTL, reg_data); in em_init_hw()
1780 reg_data = E1000_READ_REG(hw, TCTL_EXT); in em_init_hw()
1781 reg_data in em_init_hw()
2555 uint32_t reg_data; em_copper_link_ggp_setup() local
3173 uint16_t reg_data; em_setup_copper_link() local
3321 uint16_t reg_data; em_configure_kmrn_for_10_100() local
3355 uint16_t reg_data; em_configure_kmrn_for_1000() local
11082 uint16_t word_addr, reg_data, reg_addr; em_init_lcd_from_nvm_config_region() local
11123 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask; em_init_lcd_from_nvm() local
[all...]
/openbsd-src/sys/dev/pci/drm/amd/amdkfd/
H A Dkfd_packet_manager_v9.c295 uint32_t reg_data = 0; in pm_set_grace_period_v9() local
302 &reg_data); in pm_set_grace_period_v9()
305 reg_data = pm->dqm->wait_times; in pm_set_grace_period_v9()
319 packet->data = reg_data; in pm_set_grace_period_v9()
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dce112/
H A Ddce112_compressor.c420 uint32_t reg_data; in dce112_compressor_disable_fbc() local
422 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); in dce112_compressor_disable_fbc()
423 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN); in dce112_compressor_disable_fbc()
424 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data); in dce112_compressor_disable_fbc()
/openbsd-src/sys/dev/pci/drm/amd/pm/powerplay/smumgr/
H A Dsmu8_smumgr.c176 uint32_t reg_data; in smu8_load_mec_firmware() local
206 reg_data = lower_32_bits(info.mc_addr) & in smu8_load_mec_firmware()
208 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data); in smu8_load_mec_firmware()
210 reg_data = upper_32_bits(info.mc_addr) & in smu8_load_mec_firmware()
212 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data); in smu8_load_mec_firmware()
/openbsd-src/sys/dev/pci/drm/i915/gvt/
H A Dedid.c297 u32 reg_data = 0; in gmbus3_mmio_read() local
310 reg_data |= (byte_data << (i << 3)); in gmbus3_mmio_read()
313 memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count); in gmbus3_mmio_read()
/openbsd-src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dppatomctrl.c54 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) in atomctrl_retrieve_ac_timing() local
59 while (*(uint32_t *)reg_data != END_OF_REG_DATA_BLOCK && in atomctrl_retrieve_ac_timing()
61 tmem_id = (uint8_t)((*(uint32_t *)reg_data & MEM_ID_MASK) >> MEM_ID_SHIFT); in atomctrl_retrieve_ac_timing()
65 (uint32_t)((*(uint32_t *)reg_data & CLOCK_RANGE_MASK) >> in atomctrl_retrieve_ac_timing()
72 (uint32_t)*((uint32_t *)reg_data + j); in atomctrl_retrieve_ac_timing()
84 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) in atomctrl_retrieve_ac_timing()
85 ((uint8_t *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)) ; in atomctrl_retrieve_ac_timing()
88 PP_ASSERT_WITH_CODE((*(uint32_t *)reg_data == END_OF_REG_DATA_BLOCK), in atomctrl_retrieve_ac_timing()
/openbsd-src/gnu/llvm/lldb/source/Utility/
H A DRegisterValue.cpp59 DataExtractor reg_data; in GetAsMemoryData() local
60 if (!GetData(reg_data)) { in GetAsMemoryData()
67 reg_data.CopyByteOrderedData(0, // src offset in GetAsMemoryData()

12