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Searched refs:pipe (Results 1 – 25 of 707) sorted by relevance

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/openbsd-src/sys/dev/pci/drm/i915/display/
H A Dintel_vdsc_regs.h31 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
45 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
54 #define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
57 #define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
66 #define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
69 #define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
82 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
85 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
106 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
109 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ argument
[all …]
H A Dskl_watermark_regs.h13 #define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ argument
41 #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe) argument
74 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) argument
75 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) argument
76 #define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) argument
77 #define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) argument
78 #define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) argument
79 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) argument
80 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) argument
81 #define _PLANE_WM_BASE(pipe, plane) \ argument
[all …]
H A Dintel_display_irq.c26 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) in intel_handle_vblank() argument
28 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); in intel_handle_vblank()
108 enum pipe pipe, u32 interrupt_mask, in bdw_update_pipe_irq() argument
120 new_val = dev_priv->de_irq_mask[pipe]; in bdw_update_pipe_irq()
124 if (new_val != dev_priv->de_irq_mask[pipe]) { in bdw_update_pipe_irq()
125 dev_priv->de_irq_mask[pipe] = new_val; in bdw_update_pipe_irq()
126 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in bdw_update_pipe_irq()
127 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
132 enum pipe pipe, u32 bits) in bdw_enable_pipe_irq() argument
134 bdw_update_pipe_irq(i915, pipe, bits, bits); in bdw_enable_pipe_irq()
[all …]
H A Dintel_dsb_regs.h13 #define DSBSL_INSTANCE(pipe, id) (_DSBSL_INSTANCE_BASE + \ argument
14 (pipe) * 0x1000 + (id) * 0x100)
15 #define DSB_HEAD(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x0) argument
16 #define DSB_TAIL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x4) argument
17 #define DSB_CTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x8) argument
25 #define DSB_MMIOCTRL(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0xc) argument
31 #define DSB_POLLFUNC(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x10) argument
37 #define DSB_DEBUG(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x14) argument
38 #define DSB_POLLMASK(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c) argument
39 #define DSB_STATUS(pipe, id) _MMIO(DSBSL_INSTANCE(pipe, id) + 0x24) argument
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H A Dintel_pch_display.c21 enum pipe pch_transcoder) in intel_has_pch_trancoder()
27 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) in intel_crtc_pch_transcoder()
34 return crtc->pipe; in intel_crtc_pch_transcoder()
38 enum pipe pipe, enum port port, in assert_pch_dp_disabled() argument
41 enum pipe port_pipe; in assert_pch_dp_disabled()
46 I915_STATE_WARN(dev_priv, state && port_pipe == pipe, in assert_pch_dp_disabled()
48 port_name(port), pipe_name(pipe)); in assert_pch_dp_disabled()
57 enum pipe pipe, enum port port, in assert_pch_hdmi_disabled() argument
60 enum pipe port_pipe; in assert_pch_hdmi_disabled()
65 I915_STATE_WARN(dev_priv, state && port_pipe == pipe, in assert_pch_hdmi_disabled()
[all …]
H A Dintel_fifo_underrun.c62 enum pipe pipe; in ivb_can_enable_err_int() local
66 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
67 crtc = intel_crtc_for_pipe(dev_priv, pipe); in ivb_can_enable_err_int()
79 enum pipe pipe; in cpt_can_enable_serr_int() local
84 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
85 crtc = intel_crtc_for_pipe(dev_priv, pipe); in cpt_can_enable_serr_int()
97 i915_reg_t reg = PIPESTAT(crtc->pipe); in i9xx_check_fifo_underruns()
105 enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
109 trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
110 drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe)); in i9xx_check_fifo_underruns()
[all …]
H A Dintel_fdi.c23 enum pipe pipe, bool state) in assert_fdi_tx() argument
34 enum transcoder cpu_transcoder = (enum transcoder)pipe; in assert_fdi_tx()
37 cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; in assert_fdi_tx()
44 void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe) in assert_fdi_tx_enabled() argument
46 assert_fdi_tx(i915, pipe, true); in assert_fdi_tx_enabled()
49 void assert_fdi_tx_disabled(struct drm_i915_private *i915, enum pipe pipe) in assert_fdi_tx_disabled() argument
51 assert_fdi_tx(i915, pipe, false); in assert_fdi_tx_disabled()
55 enum pipe pipe, bool state) in assert_fdi_rx() argument
59 cur_state = intel_de_read(dev_priv, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE; in assert_fdi_rx()
65 void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe) in assert_fdi_rx_enabled() argument
[all …]
H A Dintel_audio_regs.h20 #define IBX_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _IBX_HDMIW_HDMIEDID_A, \ argument
24 #define IBX_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CNTL_ST_A, \ argument
35 #define CPT_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _CPT_HDMIW_HDMIEDID_A, _CPT_HDMIW_HDMIEDID_B) argument
38 #define CPT_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CNTL_ST_A, _CPT_AUD_CNTL_ST_B) argument
43 #define VLV_HDMIW_HDMIEDID(pipe) _MMIO_PIPE(pipe, _VLV_HDMIW_HDMIEDID_A, _VLV_HDMIW_HDMIEDID_B) argument
46 #define VLV_AUD_CNTL_ST(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CNTL_ST_A, _VLV_AUD_CNTL_ST_B) argument
51 #define IBX_AUD_CFG(pipe) _MMIO_PIPE(pipe, _IBX_AUD_CONFIG_A, _IBX_AUD_CONFIG_B) argument
54 #define CPT_AUD_CFG(pipe) _MMIO_PIPE(pipe, _CPT_AUD_CONFIG_A, _CPT_AUD_CONFIG_B) argument
57 #define VLV_AUD_CFG(pipe) _MMIO_PIPE(pipe, _VLV_AUD_CONFIG_A, _VLV_AUD_CONFIG_B) argument
137 #define HBLANK_EARLY_ENABLE_ICL(pipe) (0x1 << (20 - (pipe))) argument
[all …]
H A Dintel_dpio_phy.c669 enum dpio_channel vlv_pipe_to_channel(enum pipe pipe) in vlv_pipe_to_channel() argument
671 switch (pipe) { in vlv_pipe_to_channel()
673 MISSING_CASE(pipe); in vlv_pipe_to_channel()
692 enum pipe pipe = crtc->pipe; in chv_set_phy_signal_level() local
699 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
703 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_set_phy_signal_level()
706 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
710 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_set_phy_signal_level()
713 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_set_phy_signal_level()
716 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_set_phy_signal_level()
[all …]
H A Dintel_fdi.h9 enum pipe;
32 void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe);
33 void assert_fdi_tx_disabled(struct drm_i915_private *i915, enum pipe pipe);
34 void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe);
35 void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe);
36 void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
37 void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
38 void assert_fdi_rx_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
H A Dintel_sprite.c138 enum pipe pipe = plane->pipe; in vlv_sprite_update_clrc() local
165 intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id), in vlv_sprite_update_clrc()
167 intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id), in vlv_sprite_update_clrc()
341 enum pipe pipe = plane->pipe; in vlv_sprite_update_gamma() local
355 intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1), in vlv_sprite_update_gamma()
365 enum pipe pipe = plane->pipe; in vlv_sprite_update_noarm() local
372 intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id), in vlv_sprite_update_noarm()
374 intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id), in vlv_sprite_update_noarm()
376 intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id), in vlv_sprite_update_noarm()
386 enum pipe pipe = plane->pipe; in vlv_sprite_update_arm() local
[all …]
H A Dintel_pipe_crc.c76 enum pipe pipe, in i9xx_pipe_crc_auto_source() argument
92 if (crtc->pipe != pipe) in i9xx_pipe_crc_auto_source()
126 enum pipe pipe, in vlv_pipe_crc_ctl_reg() argument
133 i9xx_pipe_crc_auto_source(dev_priv, pipe, source); in vlv_pipe_crc_ctl_reg()
173 switch (pipe) { in vlv_pipe_crc_ctl_reg()
193 enum pipe pipe, in i9xx_pipe_crc_ctl_reg() argument
198 i9xx_pipe_crc_auto_source(dev_priv, pipe, source); in i9xx_pipe_crc_ctl_reg()
230 enum pipe pipe) in vlv_undo_pipe_scramble_reset() argument
234 switch (pipe) { in vlv_undo_pipe_scramble_reset()
309 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
[all …]
H A Dintel_color.c206 enum pipe pipe = crtc->pipe; in ilk_update_pipe_csc() local
208 intel_de_write_fw(i915, PIPE_CSC_PREOFF_HI(pipe), csc->preoff[0]); in ilk_update_pipe_csc()
209 intel_de_write_fw(i915, PIPE_CSC_PREOFF_ME(pipe), csc->preoff[1]); in ilk_update_pipe_csc()
210 intel_de_write_fw(i915, PIPE_CSC_PREOFF_LO(pipe), csc->preoff[2]); in ilk_update_pipe_csc()
212 intel_de_write_fw(i915, PIPE_CSC_COEFF_RY_GY(pipe), in ilk_update_pipe_csc()
214 intel_de_write_fw(i915, PIPE_CSC_COEFF_BY(pipe), in ilk_update_pipe_csc()
217 intel_de_write_fw(i915, PIPE_CSC_COEFF_RU_GU(pipe), in ilk_update_pipe_csc()
219 intel_de_write_fw(i915, PIPE_CSC_COEFF_BU(pipe), in ilk_update_pipe_csc()
222 intel_de_write_fw(i915, PIPE_CSC_COEFF_RV_GV(pipe), in ilk_update_pipe_csc()
224 intel_de_write_fw(i915, PIPE_CSC_COEFF_BV(pipe), in ilk_update_pipe_csc()
[all …]
H A Dintel_fdi_regs.h28 #define FDI_RX_CHICKEN(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN) argument
33 #define FDI_TX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL) argument
83 #define FDI_RX_CTL(pipe) _MMIO_PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL) argument
119 #define FDI_RX_MISC(pipe) _MMIO_PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC) argument
125 #define FDI_RX_TUSIZE1(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1) argument
126 #define FDI_RX_TUSIZE2(pipe) _MMIO_PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2) argument
145 #define FDI_RX_IIR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR) argument
146 #define FDI_RX_IMR(pipe) _MMIO_PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR) argument
H A Dintel_dpll.h16 enum pipe;
30 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
32 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
35 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe);
37 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe);
44 void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
45 void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
H A Dintel_dpll.c1214 if (crtc->pipe != PIPE_A) in vlv_compute_dpll()
1232 if (crtc->pipe != PIPE_A) in chv_compute_dpll()
1586 enum pipe pipe = crtc->pipe; in i9xx_enable_pll() local
1593 assert_pps_unlocked(dev_priv, pipe); in i9xx_enable_pll()
1595 intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0); in i9xx_enable_pll()
1596 intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1); in i9xx_enable_pll()
1603 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1604 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1607 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1611 intel_de_write(dev_priv, DPLL_MD(pipe), in i9xx_enable_pll()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_resource_helpers.c129 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; in dcn32_merge_pipes_for_subvp() local
134 if (pipe->prev_odm_pipe) { in dcn32_merge_pipes_for_subvp()
136 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe; in dcn32_merge_pipes_for_subvp()
137 if (pipe->next_odm_pipe) in dcn32_merge_pipes_for_subvp()
138 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe; in dcn32_merge_pipes_for_subvp()
140 pipe->bottom_pipe = NULL; in dcn32_merge_pipes_for_subvp()
141 pipe->next_odm_pipe = NULL; in dcn32_merge_pipes_for_subvp()
142 pipe->plane_state = NULL; in dcn32_merge_pipes_for_subvp()
143 pipe->stream = NULL; in dcn32_merge_pipes_for_subvp()
144 pipe->top_pipe = NULL; in dcn32_merge_pipes_for_subvp()
[all …]
/openbsd-src/sys/dev/pci/drm/
H A Ddrm_vblank.c157 drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,
169 static void store_vblank(struct drm_device *dev, unsigned int pipe, in store_vblank() argument
173 struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; in store_vblank()
185 static u32 drm_max_vblank_count(struct drm_device *dev, unsigned int pipe) in drm_max_vblank_count() argument
187 struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; in drm_max_vblank_count()
196 static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe) in drm_vblank_no_hw_counter() argument
198 drm_WARN_ON_ONCE(dev, drm_max_vblank_count(dev, pipe) != 0); in drm_vblank_no_hw_counter()
202 static u32 __get_vblank_counter(struct drm_device *dev, unsigned int pipe) in __get_vblank_counter() argument
205 struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe); in __get_vblank_counter()
215 return dev->driver->get_vblank_counter(dev, pipe); in __get_vblank_counter()
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/openbsd-src/gnu/usr.bin/perl/dist/IO/t/
H A Dio_pipe.t40 my $pipe;
45 $pipe = IO::Pipe->new()->reader($perl, '-e', 'print qq(not ok 1\n)');
46 while (<$pipe>) {
50 $pipe->close or print "# \$!=$!\nnot ";
53 $pipe = IO::Pipe->new()->writer($perl, '-pe', $cmd);
54 print $pipe "not ok 3\n" ;
55 $pipe->close or print "# \$!=$!\nnot ";
66 $pipe = IO::Pipe->new();
72 $pipe->writer;
73 print $pipe "Xk 5\n";
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/openbsd-src/sys/dev/pci/drm/i915/
H A Di915_reg.h51 * instances, for example one per pipe, port, transcoder, etc. Register groups
108 * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
151 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) argument
198 #define DPIO_PHY(pipe) ((pipe) >> 1) argument
201 * Per pipe/PLL DPIO regs
992 #define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * argument
994 ERR_INT_FIFO_UNDERRUN(pipe) global() argument
1415 DPLL(pipe) global() argument
1514 DPLL_MD(pipe) global() argument
1559 FP0(pipe) global() argument
1560 FP1(pipe) global() argument
1743 PALETTE(pipe,i) global() argument
1827 CLKGATE_DIS_PSL(pipe) global() argument
1834 CLKGATE_DIS_PSL_EXT(pipe) global() argument
1914 PIPE_CRC_CTL(pipe) global() argument
1915 PIPE_CRC_RES_1_IVB(pipe) global() argument
1916 PIPE_CRC_RES_2_IVB(pipe) global() argument
1917 PIPE_CRC_RES_3_IVB(pipe) global() argument
1918 PIPE_CRC_RES_4_IVB(pipe) global() argument
1919 PIPE_CRC_RES_5_IVB(pipe) global() argument
1921 PIPE_CRC_RES_RED(pipe) global() argument
1922 PIPE_CRC_RES_GREEN(pipe) global() argument
1923 PIPE_CRC_RES_BLUE(pipe) global() argument
1924 PIPE_CRC_RES_RES1_I915(pipe) global() argument
1925 PIPE_CRC_RES_RES2_G4X(pipe) global() argument
2002 PIPESRC(pipe) global() argument
2107 ADPA_PIPE_SEL(pipe) global() argument
2110 ADPA_PIPE_SEL_CPT(pipe) global() argument
2260 SDVO_PIPE_SEL(pipe) global() argument
2302 SDVO_PIPE_SEL_CPT(pipe) global() argument
2307 SDVO_PIPE_SEL_CHV(pipe) global() argument
2358 PFIT_PIPE(pipe) global() argument
2402 DP_PIPE_SEL(pipe) global() argument
2405 DP_PIPE_SEL_IVB(pipe) global() argument
2408 DP_PIPE_SEL_CHV(pipe) global() argument
2524 PIPE_DATA_M_G4X(pipe) global() argument
2525 PIPE_DATA_N_G4X(pipe) global() argument
2526 PIPE_LINK_M_G4X(pipe) global() argument
2527 PIPE_LINK_N_G4X(pipe) global() argument
2643 PIPEDSL(pipe) global() argument
2644 PIPEFRAME(pipe) global() argument
2645 PIPEFRAMEPIXEL(pipe) global() argument
2646 PIPESTAT(pipe) global() argument
2650 PIPEGCMAX(pipe,i) global() argument
2653 PIPE_ARB_CTL(pipe) global() argument
2685 PIPE_MISC(pipe) global() argument
2694 PIPE_MISC2(pipe) global() argument
2701 SKL_BOTTOM_COLOR(pipe) global() argument
2704 ICL_PIPESTATUS(pipe) global() argument
2927 VLV_DDL(pipe) global() argument
2940 CBR_DPLLBMD_PIPE(pipe) global() argument
2979 WM0_PIPE_ILK(pipe) global() argument
3034 PIPE_FRMCOUNT_G4X(pipe) global() argument
3035 PIPE_FLIPCOUNT_G4X(pipe) global() argument
3054 MCURSOR_PIPE_SEL(pipe) global() argument
3094 CURCNTR(pipe) global() argument
3095 CURBASE(pipe) global() argument
3096 CURPOS(pipe) global() argument
3097 CURSIZE(pipe) global() argument
3098 CUR_FBC_CTL(pipe) global() argument
3099 CUR_CHICKEN(pipe) global() argument
3100 CURSURFLIVE(pipe) global() argument
3124 DISP_PIPE_SEL(pipe) global() argument
3195 CHV_BLEND(pipe) global() argument
3196 CHV_CANVAS(pipe) global() argument
3327 DVSCNTR(pipe) global() argument
3328 DVSLINOFF(pipe) global() argument
3329 DVSSTRIDE(pipe) global() argument
3330 DVSPOS(pipe) global() argument
3331 DVSSURF(pipe) global() argument
3332 DVSKEYMAX(pipe) global() argument
3333 DVSSIZE(pipe) global() argument
3334 DVSSCALE(pipe) global() argument
3335 DVSTILEOFF(pipe) global() argument
3336 DVSKEYVAL(pipe) global() argument
3337 DVSKEYMSK(pipe) global() argument
3338 DVSSURFLIVE(pipe) global() argument
3339 DVSGAMC_G4X(pipe,i) global() argument
3340 DVSGAMC_ILK(pipe,i) global() argument
3341 DVSGAMCMAX_ILK(pipe,i) global() argument
3426 SPRCTL(pipe) global() argument
3427 SPRLINOFF(pipe) global() argument
3428 SPRSTRIDE(pipe) global() argument
3429 SPRPOS(pipe) global() argument
3430 SPRSIZE(pipe) global() argument
3431 SPRKEYVAL(pipe) global() argument
3432 SPRKEYMSK(pipe) global() argument
3433 SPRSURF(pipe) global() argument
3434 SPRKEYMAX(pipe) global() argument
3435 SPRTILEOFF(pipe) global() argument
3436 SPROFFSET(pipe) global() argument
3437 SPRSCALE(pipe) global() argument
3438 SPRGAMC(pipe,i) global() argument
3439 SPRGAMC16(pipe,i) global() argument
3440 SPRGAMC17(pipe,i) global() argument
3441 SPRSURFLIVE(pipe) global() argument
3524 _VLV_SPR(pipe,plane_id,reg_a,reg_b) global() argument
3526 _MMIO_VLV_SPR(pipe,plane_id,reg_a,reg_b) global() argument
3529 SPCNTR(pipe,plane_id) global() argument
3530 SPLINOFF(pipe,plane_id) global() argument
3531 SPSTRIDE(pipe,plane_id) global() argument
3532 SPPOS(pipe,plane_id) global() argument
3533 SPSIZE(pipe,plane_id) global() argument
3534 SPKEYMINVAL(pipe,plane_id) global() argument
3535 SPKEYMSK(pipe,plane_id) global() argument
3536 SPSURF(pipe,plane_id) global() argument
3537 SPKEYMAXVAL(pipe,plane_id) global() argument
3538 SPTILEOFF(pipe,plane_id) global() argument
3539 SPCONSTALPHA(pipe,plane_id) global() argument
3540 SPSURFLIVE(pipe,plane_id) global() argument
3541 SPCLRC0(pipe,plane_id) global() argument
3542 SPCLRC1(pipe,plane_id) global() argument
3543 SPGAMC(pipe,plane_id,i) global() argument
3760 _PLANE_CC_VAL_1(pipe,dw) global() argument
3761 _PLANE_CC_VAL_2(pipe,dw) global() argument
3762 PLANE_CC_VAL(pipe,plane,dw) global() argument
3772 _PLANE_INPUT_CSC_RY_GY_1(pipe) global() argument
3775 _PLANE_INPUT_CSC_RY_GY_2(pipe) global() argument
3779 PLANE_INPUT_CSC_COEFF(pipe,plane,index) global() argument
3789 _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) global() argument
3792 _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) global() argument
3795 PLANE_INPUT_CSC_PREOFF(pipe,plane,index) global() argument
3805 _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) global() argument
3808 _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) global() argument
3811 PLANE_INPUT_CSC_POSTOFF(pipe,plane,index) global() argument
3818 _PLANE_CTL_1(pipe) global() argument
3819 _PLANE_CTL_2(pipe) global() argument
3820 _PLANE_CTL_3(pipe) global() argument
3821 PLANE_CTL(pipe,plane) global() argument
3827 _PLANE_STRIDE_1(pipe) global() argument
3829 _PLANE_STRIDE_2(pipe) global() argument
3831 _PLANE_STRIDE_3(pipe) global() argument
3833 PLANE_STRIDE(pipe,plane) global() argument
3839 _PLANE_POS_1(pipe) global() argument
3840 _PLANE_POS_2(pipe) global() argument
3841 _PLANE_POS_3(pipe) global() argument
3842 PLANE_POS(pipe,plane) global() argument
3848 _PLANE_SIZE_1(pipe) global() argument
3849 _PLANE_SIZE_2(pipe) global() argument
3850 _PLANE_SIZE_3(pipe) global() argument
3851 PLANE_SIZE(pipe,plane) global() argument
3857 _PLANE_SURF_1(pipe) global() argument
3858 _PLANE_SURF_2(pipe) global() argument
3859 _PLANE_SURF_3(pipe) global() argument
3860 PLANE_SURF(pipe,plane) global() argument
3865 _PLANE_OFFSET_1(pipe) global() argument
3866 _PLANE_OFFSET_2(pipe) global() argument
3867 PLANE_OFFSET(pipe,plane) global() argument
3872 _PLANE_KEYVAL_1(pipe) global() argument
3873 _PLANE_KEYVAL_2(pipe) global() argument
3874 PLANE_KEYVAL(pipe,plane) global() argument
3879 _PLANE_KEYMSK_1(pipe) global() argument
3880 _PLANE_KEYMSK_2(pipe) global() argument
3881 PLANE_KEYMSK(pipe,plane) global() argument
3886 _PLANE_KEYMAX_1(pipe) global() argument
3887 _PLANE_KEYMAX_2(pipe) global() argument
3888 PLANE_KEYMAX(pipe,plane) global() argument
3893 _PLANE_SURFLIVE_1(pipe) global() argument
3894 _PLANE_SURFLIVE_2(pipe) global() argument
3895 PLANE_SURFLIVE(pipe,plane) global() argument
3900 _PLANE_CHICKEN_1(pipe) global() argument
3901 _PLANE_CHICKEN_2(pipe) global() argument
3902 PLANE_CHICKEN(pipe,plane) global() argument
3907 _PLANE_AUX_DIST_1(pipe) global() argument
3909 _PLANE_AUX_DIST_2(pipe) global() argument
3911 PLANE_AUX_DIST(pipe,plane) global() argument
3916 _PLANE_AUX_OFFSET_1(pipe) global() argument
3918 _PLANE_AUX_OFFSET_2(pipe) global() argument
3920 PLANE_AUX_OFFSET(pipe,plane) global() argument
3925 _PLANE_CUS_CTL_1(pipe) global() argument
3927 _PLANE_CUS_CTL_2(pipe) global() argument
3929 PLANE_CUS_CTL(pipe,plane) global() argument
3935 _PLANE_COLOR_CTL_1(pipe) global() argument
3937 _PLANE_COLOR_CTL_2(pipe) global() argument
3939 PLANE_COLOR_CTL(pipe,plane) global() argument
4013 PF_PIPE_SEL_IVB(pipe) global() argument
4036 PF_CTL(pipe) global() argument
4037 PF_WIN_SZ(pipe) global() argument
4038 PF_WIN_POS(pipe) global() argument
4039 PF_VSCALE(pipe) global() argument
4040 PF_HSCALE(pipe) global() argument
4182 SKL_PS_CTRL(pipe,id) global() argument
4185 SKL_PS_PWR_GATE(pipe,id) global() argument
4188 SKL_PS_WIN_POS(pipe,id) global() argument
4191 SKL_PS_WIN_SZ(pipe,id) global() argument
4194 SKL_PS_VSCALE(pipe,id) global() argument
4197 SKL_PS_HSCALE(pipe,id) global() argument
4200 SKL_PS_VPHASE(pipe,id) global() argument
4203 SKL_PS_HPHASE(pipe,id) global() argument
4206 SKL_PS_ECC_STAT(pipe,id) global() argument
4209 GLK_PS_COEF_INDEX_SET(pipe,id,set) global() argument
4213 GLK_PS_COEF_DATA_SET(pipe,id,set) global() argument
4220 LGC_PALETTE(pipe,i) global() argument
4237 PREC_PALETTE(pipe,i) global() argument
4241 PREC_PIPEGCMAX(pipe,i) global() argument
4245 GAMMA_MODE(pipe) global() argument
4283 DE_PIPE_VBLANK(pipe) global() argument
4289 DE_PIPE_CRC_DONE(pipe) global() argument
4291 DE_PIPE_FIFO_UNDERRUN(pipe) global() argument
4310 DE_PIPE_VBLANK_IVB(pipe) global() argument
4334 GEN8_DE_PIPE_IRQ(pipe) global() argument
4357 GEN8_DE_PIPE_ISR(pipe) global() argument
4358 GEN8_DE_PIPE_IMR(pipe) global() argument
4359 GEN8_DE_PIPE_IIR(pipe) global() argument
4360 GEN8_DE_PIPE_IER(pipe) global() argument
4610 CHICKEN_PIPESL_1(pipe) global() argument
4743 PIPE_CHICKEN(pipe) global() argument
4868 SERR_INT_TRANS_FIFO_UNDERRUN(pipe) global() argument
4999 TRANS_DPLLB_SEL(pipe) global() argument
5000 TRANS_DPLLA_SEL(pipe) global() argument
5001 TRANS_DPLL_ENABLE(pipe) global() argument
5046 TVIDEO_DIP_CTL(pipe) global() argument
5047 TVIDEO_DIP_DATA(pipe) global() argument
5048 TVIDEO_DIP_GCP(pipe) global() argument
5063 VLV_TVIDEO_DIP_CTL(pipe) global() argument
5066 VLV_TVIDEO_DIP_DATA(pipe) global() argument
5069 VLV_TVIDEO_DIP_GCP(pipe) global() argument
5139 PCH_TRANS_HTOTAL(pipe) global() argument
5140 PCH_TRANS_HBLANK(pipe) global() argument
5141 PCH_TRANS_HSYNC(pipe) global() argument
5142 PCH_TRANS_VTOTAL(pipe) global() argument
5143 PCH_TRANS_VBLANK(pipe) global() argument
5144 PCH_TRANS_VSYNC(pipe) global() argument
5145 PCH_TRANS_VSYNCSHIFT(pipe) global() argument
5156 PCH_TRANS_DATA_M1(pipe) global() argument
5157 PCH_TRANS_DATA_N1(pipe) global() argument
5158 PCH_TRANS_DATA_M2(pipe) global() argument
5159 PCH_TRANS_DATA_N2(pipe) global() argument
5160 PCH_TRANS_LINK_M1(pipe) global() argument
5161 PCH_TRANS_LINK_N1(pipe) global() argument
5162 PCH_TRANS_LINK_M2(pipe) global() argument
5163 PCH_TRANS_LINK_N2(pipe) global() argument
5167 PCH_TRANSCONF(pipe) global() argument
5185 TRANS_CHICKEN1(pipe) global() argument
5191 TRANS_CHICKEN2(pipe) global() argument
5212 FDI_PHASE_SYNC_OVR(pipe) global() argument
5213 FDI_PHASE_SYNC_EN(pipe) global() argument
5269 TRANS_DP_CTL(pipe) global() argument
5753 DDI_DP_COMP_CTL(pipe) global() argument
5766 DDI_DP_COMP_PAT(pipe,i) global() argument
5937 BXT_CDCLK_CD2X_PIPE(pipe) global() argument
5940 ICL_CDCLK_CD2X_PIPE(pipe) global() argument
5942 TGL_CDCLK_CD2X_PIPE(pipe) global() argument
6247 WM_LINETIME(pipe) global() argument
6308 PIPE_CSC_COEFF_RY_GY(pipe) global() argument
6309 PIPE_CSC_COEFF_BY(pipe) global() argument
6310 PIPE_CSC_COEFF_RU_GU(pipe) global() argument
6311 PIPE_CSC_COEFF_BU(pipe) global() argument
6312 PIPE_CSC_COEFF_RV_GV(pipe) global() argument
6313 PIPE_CSC_COEFF_BV(pipe) global() argument
6314 PIPE_CSC_MODE(pipe) global() argument
6315 PIPE_CSC_PREOFF_HI(pipe) global() argument
6316 PIPE_CSC_PREOFF_ME(pipe) global() argument
6317 PIPE_CSC_PREOFF_LO(pipe) global() argument
6318 PIPE_CSC_POSTOFF_HI(pipe) global() argument
6319 PIPE_CSC_POSTOFF_ME(pipe) global() argument
6320 PIPE_CSC_POSTOFF_LO(pipe) global() argument
6349 PIPE_CSC_OUTPUT_COEFF_RY_GY(pipe) global() argument
6352 PIPE_CSC_OUTPUT_COEFF_BY(pipe) global() argument
6355 PIPE_CSC_OUTPUT_COEFF_RU_GU(pipe) global() argument
6358 PIPE_CSC_OUTPUT_COEFF_BU(pipe) global() argument
6361 PIPE_CSC_OUTPUT_COEFF_RV_GV(pipe) global() argument
6364 PIPE_CSC_OUTPUT_COEFF_BV(pipe) global() argument
6367 PIPE_CSC_OUTPUT_PREOFF_HI(pipe) global() argument
6370 PIPE_CSC_OUTPUT_PREOFF_ME(pipe) global() argument
6373 PIPE_CSC_OUTPUT_PREOFF_LO(pipe) global() argument
6376 PIPE_CSC_OUTPUT_POSTOFF_HI(pipe) global() argument
6379 PIPE_CSC_OUTPUT_POSTOFF_ME(pipe) global() argument
6382 PIPE_CSC_OUTPUT_POSTOFF_LO(pipe) global() argument
6408 PREC_PAL_INDEX(pipe) global() argument
6409 PREC_PAL_DATA(pipe) global() argument
6410 PREC_PAL_GC_MAX(pipe,i) global() argument
6411 PREC_PAL_EXT_GC_MAX(pipe,i) global() argument
6412 PREC_PAL_EXT2_GC_MAX(pipe,i) global() argument
6424 PRE_CSC_GAMC_INDEX(pipe) global() argument
6425 PRE_CSC_GAMC_DATA(pipe) global() argument
6438 PREC_PAL_MULTI_SEG_INDEX(pipe) global() argument
6441 PREC_PAL_MULTI_SEG_DATA(pipe) global() argument
6454 _PLANE_CSC_RY_GY_1(pipe) global() argument
6456 _PLANE_CSC_RY_GY_2(pipe) global() argument
6458 PLANE_CSC_COEFF(pipe,plane,index) global() argument
6468 _PLANE_CSC_PREOFF_HI_1(pipe) global() argument
6470 _PLANE_CSC_PREOFF_HI_2(pipe) global() argument
6472 PLANE_CSC_PREOFF(pipe,plane,index) global() argument
6482 _PLANE_CSC_POSTOFF_HI_1(pipe) global() argument
6484 _PLANE_CSC_POSTOFF_HI_2(pipe) global() argument
6486 PLANE_CSC_POSTOFF(pipe,plane,index) global() argument
6497 PIPE_WGC_C01_C00(pipe) global() argument
6498 PIPE_WGC_C02(pipe) global() argument
6499 PIPE_WGC_C11_C10(pipe) global() argument
6500 PIPE_WGC_C12(pipe) global() argument
6501 PIPE_WGC_C21_C20(pipe) global() argument
6502 PIPE_WGC_C22(pipe) global() argument
6536 CGM_PIPE_CSC_COEFF01(pipe) global() argument
6537 CGM_PIPE_CSC_COEFF23(pipe) global() argument
6538 CGM_PIPE_CSC_COEFF45(pipe) global() argument
6539 CGM_PIPE_CSC_COEFF67(pipe) global() argument
6540 CGM_PIPE_CSC_COEFF8(pipe) global() argument
6541 CGM_PIPE_DEGAMMA(pipe,i,w) global() argument
6542 CGM_PIPE_GAMMA(pipe,i,w) global() argument
6543 CGM_PIPE_MODE(pipe) global() argument
6559 PIPE_FRMTMSTMP(pipe) global() argument
6565 PIPE_FLIPTMSTMP(pipe) global() argument
6571 PIPE_FLIPDONETIMSTMP(pipe) global() argument
6575 VLV_PIPE_MSA_MISC(pipe) global() argument
[all...]
H A Dvlv_sideband_reg.h49 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) argument
50 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) argument
51 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) argument
52 #define DP_SSC_CLK_GATE(pipe) _DP_SSC(0x1, (pipe)) argument
53 #define DP_SSC_RESET(pipe) _DP_SSC(0x2, (pipe)) argument
54 #define DP_SSC_PWR_GATE(pipe) _DP_SSC(0x3, (pipe)) argument
55 #define _DP_SSS(val, pipe) ((val) << (2 * (pipe) + 16)) argument
56 #define DP_SSS_MASK(pipe) _DP_SSS(0x3, (pipe)) argument
57 #define DP_SSS_PWR_ON(pipe) _DP_SSS(0x0, (pipe)) argument
58 #define DP_SSS_CLK_GATE(pipe) _DP_SSS(0x1, (pipe)) argument
[all …]
/openbsd-src/sys/dev/usb/
H A Dusbdi.c57 void usbd_start_next(struct usbd_pipe *pipe);
148 usbd_dump_queue(struct usbd_pipe *pipe) in usbd_dump_queue() argument
152 printf("%s: pipe=%p\n", __func__, pipe); in usbd_dump_queue()
153 SIMPLEQ_FOREACH(xfer, &pipe->queue, next) { in usbd_dump_queue()
159 usbd_dump_pipe(struct usbd_pipe *pipe) in usbd_dump_pipe() argument
161 printf("%s: pipe=%p\n", __func__, pipe); in usbd_dump_pipe()
162 if (pipe == NULL) in usbd_dump_pipe()
164 usbd_dump_iface(pipe->iface); in usbd_dump_pipe()
165 usbd_dump_device(pipe->device); in usbd_dump_pipe()
166 usbd_dump_endpoint(pipe->endpoint); in usbd_dump_pipe()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c313 struct pipe_ctx *pipe; in dcn314_populate_dml_pipes_from_context_fpu() local
328 pipe = &res_ctx->pipe_ctx[i]; in dcn314_populate_dml_pipes_from_context_fpu()
329 timing = &pipe->stream->timing; in dcn314_populate_dml_pipes_from_context_fpu()
333 if (pipe->stream->adjust.v_total_min != 0) in dcn314_populate_dml_pipes_from_context_fpu()
334 pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; in dcn314_populate_dml_pipes_from_context_fpu()
336 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; in dcn314_populate_dml_pipes_from_context_fpu()
340 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn314_populate_dml_pipes_from_context_fpu()
341 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); in dcn314_populate_dml_pipes_from_context_fpu()
346 pipes[pipe_cnt].pipe.dest.vblank_nom = in dcn314_populate_dml_pipes_from_context_fpu()
347 max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2); in dcn314_populate_dml_pipes_from_context_fpu()
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c302 const struct pipe_ctx *pipe, in pipe_ctx_to_e2e_pipe_params() argument
308 if (pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE || in pipe_ctx_to_e2e_pipe_params()
309 pipe->plane_state->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) { in pipe_ctx_to_e2e_pipe_params()
311 input->src.hsplit_grp = pipe->pipe_idx; in pipe_ctx_to_e2e_pipe_params()
312 } else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) { in pipe_ctx_to_e2e_pipe_params()
314 } else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe in pipe_ctx_to_e2e_pipe_params()
455 dcn_bw_calc_rq_dlg_ttu(const struct dc * dc,const struct dcn_bw_internal_vars * v,struct pipe_ctx * pipe,int in_idx) dcn_bw_calc_rq_dlg_ttu() argument
710 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; hack_bounding_box() local
894 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; dcn_validate_bandwidth() local
1200 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; dcn_validate_bandwidth() local
[all...]
/openbsd-src/sys/dev/pci/drm/amd/amdgpu/
H A Dmes_v10_1.c383 enum admgpu_mes_pipe pipe) in mes_v10_1_allocate_ucode_buffer() argument
391 adev->mes.fw[pipe]->data; in mes_v10_1_allocate_ucode_buffer()
393 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + in mes_v10_1_allocate_ucode_buffer()
399 &adev->mes.ucode_fw_obj[pipe], in mes_v10_1_allocate_ucode_buffer()
400 &adev->mes.ucode_fw_gpu_addr[pipe], in mes_v10_1_allocate_ucode_buffer()
401 (void **)&adev->mes.ucode_fw_ptr[pipe]); in mes_v10_1_allocate_ucode_buffer()
407 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); in mes_v10_1_allocate_ucode_buffer()
409 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); in mes_v10_1_allocate_ucode_buffer()
410 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); in mes_v10_1_allocate_ucode_buffer()
416 enum admgpu_mes_pipe pipe) in mes_v10_1_allocate_ucode_data_buffer() argument
[all …]

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