| /openbsd-src/gnu/llvm/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 80 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
84 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | Thumb1InstrInfo.cpp | 74 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
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| H A D | ThumbRegisterInfo.cpp | 76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
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| H A D | ARMLoadStoreOptimizer.cpp | 811 MIB.addReg(Base, getDefRegState(true)) in CreateLoadStoreMulti()
827 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti()
1350 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLSMultiple()
1531 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLoadStore()
1535 .addReg(MO.getReg(), (isLd ? getDefRegState(true) in MergeBaseUpdateLoadStore()
1742 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill)) in InsertLDR_STR()
1813 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
1814 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)) in FixInvalidRegPairOp()
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| H A D | MLxExpansionPass.cpp | 298 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); in ExpandFPMLxInstruction()
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| H A D | ARMBaseRegisterInfo.cpp | 508 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
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| H A D | Thumb1FrameLowering.cpp | 1080 MIB.addReg(Reg, getDefRegState(true)); in popRegsFromStack()
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| H A D | ARMFrameLowering.cpp | 1677 MIB.addReg(Regs[i], getDefRegState(true)); in emitPopInst()
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| H A D | ARMExpandPseudoInsts.cpp | 902 getDefRegState(MI.getOperand(0).isDef()); in ExpandMQQPRLoadStore()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 236 MIB.addReg(Reg2, getDefRegState(true)) in emitLoad()
237 .addReg(Reg1, getDefRegState(true)) in emitLoad()
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| H A D | AArch64FrameLowering.cpp | 2912 MIB.addReg(Reg2, getDefRegState(true)); in restoreCalleeSavedRegisters()
2917 MIB.addReg(Reg1, getDefRegState(true)) in restoreCalleeSavedRegisters()
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| H A D | AArch64InstrInfo.cpp | 4103 .addReg(DestReg, getDefRegState(true)) in loadRegFromStackSlot()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 525 inline unsigned getDefRegState(bool B) { in getDefRegState() function
553 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) | in getRegState()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/ |
| H A D | LanaiMemAluCombiner.cpp | 260 InstrBuilder.addReg(Dest.getReg(), getDefRegState(true)); in insertMergedInstruction()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | MachineInstrBundle.cpp | 219 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | in finalizeBundle()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 1099 .addReg(Tmp, getDefRegState(true)) in fixSCCCopies()
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| H A D | SIRegisterInfo.cpp | 1525 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildSpillLoadStore()
1622 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)); in buildSpillLoadStore()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 364 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 316 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)) in emitSPUpdate()
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| H A D | X86InstrInfo.cpp | 6984 getDefRegState(ImpOp.isDef()) | in unfoldMemoryOperand()
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