Searched refs:VLSHR (Results 1 – 4 of 4) sorted by relevance
211 VLSHR, enumerator
2144 case AArch64ISD::VLSHR: { in computeKnownBitsForTargetNode()2391 MAKE_CASE(AArch64ISD::VLSHR) in getTargetNodeName()11985 (SecondOpc == AArch64ISD::VSHL || SecondOpc == AArch64ISD::VLSHR)) { in tryLowerToSLI()11990 (FirstOpc == AArch64ISD::VSHL || FirstOpc == AArch64ISD::VLSHR)) { in tryLowerToSLI()11997 bool IsShiftRight = Shift.getOpcode() == AArch64ISD::VLSHR; in tryLowerToSLI()13005 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR; in LowerVectorSRA_SRL_SHL()19056 N->getOpcode() == AArch64ISD::VLSHR); in performVectorShiftCombine()21512 case AArch64ISD::VLSHR: in PerformDAGCombine()23898 if (ShiftR->getOpcode() != AArch64ISD::VLSHR) in SimplifyDemandedBitsForTargetNode()
182 if (N.getOpcode() != AArch64ISD::VLSHR) in SelectRoundingVLShr()
666 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;