Searched refs:SuccPred (Results 1 – 2 of 2) sorted by relevance
868 for (MachineBasicBlock *SuccPred : Succ->predecessors()) { in isProfitableToTailDup()869 if (SuccPred == Succ || SuccPred == BB in isProfitableToTailDup()870 || BlockToChain[SuccPred] == &Chain in isProfitableToTailDup()871 || (BlockFilter && !BlockFilter->count(SuccPred))) in isProfitableToTailDup()873 auto Freq = MBFI->getBlockFreq(SuccPred) in isProfitableToTailDup()874 * MBPI->getEdgeProbability(SuccPred, Succ); in isProfitableToTailDup()980 for (auto *SuccPred : Succ->predecessors()) { in isTrellis() local982 if (Successors.count(SuccPred)) { in isTrellis()984 for (MachineBasicBlock *CheckSucc : SuccPred->successors()) in isTrellis()989 const BlockChain *PredChain = BlockToChain[SuccPred]; in isTrellis()[all …]
2876 for (const SDep &SuccPred : SuccSU->Preds) { in canClobberReachingPhysRegUse() local2877 if (!SuccPred.isAssignedRegDep()) in canClobberReachingPhysRegUse()2881 MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) && in canClobberReachingPhysRegUse()2882 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit())) in canClobberReachingPhysRegUse()2889 if (TRI->regsOverlap(ImpDef, SuccPred.getReg()) && in canClobberReachingPhysRegUse()2890 scheduleDAG->IsReachable(DepSU, SuccPred.getSUnit())) in canClobberReachingPhysRegUse()