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Searched refs:NoRegister (Results 1 – 25 of 89) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyReplacePhysRegs.cpp76 for (unsigned PReg = WebAssembly::NoRegister + 1; in runOnMachineFunction()
84 unsigned VReg = WebAssembly::NoRegister; in runOnMachineFunction()
88 if (VReg == WebAssembly::NoRegister) { in runOnMachineFunction()
/openbsd-src/gnu/llvm/llvm/include/llvm/MC/
H A DMCRegister.h43 static constexpr unsigned NoRegister = 0u; variable
68 assert(Val == NoRegister || isPhysicalRegister(Val)); in from()
76 bool isValid() const { return Reg != NoRegister; } in isValid()
/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp359 if (RegNum == AVR::NoRegister) { in parseRegisterName()
362 if (RegNum == AVR::NoRegister) { in parseRegisterName()
372 if (RegNum == AVR::NoRegister) in parseRegisterName()
379 int RegNum = AVR::NoRegister; in parseRegister()
393 if (RegNum == AVR::NoRegister && RestoreOnFailure) { in parseRegister()
407 if (RegNo == AVR::NoRegister) in tryParseRegisterOperand()
573 if (RegNo == AVR::NoRegister) in parseMemriOperand()
599 return (RegNo == AVR::NoRegister); in parseRegister()
609 if (RegNo == AVR::NoRegister) in tryParseRegister()
759 if (RegNum != AVR::NoRegister) { in validateTargetOperandClass()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVMakeCompressible.cpp181 return RegImmPair(RISCV::NoRegister, 0); in getRegImmPairPreventingCompression()
214 return RegImmPair(RISCV::NoRegister, 0); in getRegImmPairPreventingCompression()
265 return RISCV::NoRegister; in analyzeCompressibleUses()
279 return RISCV::NoRegister; in analyzeCompressibleUses()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUResourceUsageAnalysis.cpp210 MCPhysReg HighestVGPRReg = AMDGPU::NoRegister; in analyzeResourceUsage()
219 MCPhysReg HighestAGPRReg = AMDGPU::NoRegister; in analyzeResourceUsage()
226 Info.NumAGPR = HighestAGPRReg == AMDGPU::NoRegister in analyzeResourceUsage()
231 MCPhysReg HighestSGPRReg = AMDGPU::NoRegister; in analyzeResourceUsage()
241 Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister in analyzeResourceUsage()
244 Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister in analyzeResourceUsage()
292 case AMDGPU::NoRegister: in analyzeResourceUsage()
H A DR600RegisterInfo.cpp66 static const MCPhysReg CalleeSavedReg = R600::NoRegister;
74 return R600::NoRegister; in getFrameRegister()
H A DSIRegisterInfo.cpp90 Register TmpVGPR = AMDGPU::NoRegister;
96 Register SavedExecReg = AMDGPU::NoRegister;
404 static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister; in getCalleeSavedRegs()
621 if (ScratchRSrcReg != AMDGPU::NoRegister) { in getReservedRegs()
1200 if (Reg == AMDGPU::NoRegister) in spillVGPRtoAGPR()
1417 if (ScratchOffsetReg != AMDGPU::NoRegister && !CanClobberSCC) in buildSpillLoadStore()
1467 } else if (ScratchOffsetReg == AMDGPU::NoRegister) { in buildSpillLoadStore()
1480 if (IsFlat && SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
1633 if (SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
1654 if (!IsStore && IsAGPR && TmpIntermediateVGPR != AMDGPU::NoRegister) { in buildSpillLoadStore()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h113 MIB.addReg(ARM::NoRegister);
121 MIB.addReg(ARM::NoRegister);
178 MIB.addReg(ARM::NoRegister);
H A DThumb1FrameLowering.cpp79 if (ScratchReg == ARM::NoRegister) in emitPrologueEpilogueSPUpdate()
184 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
197 ARM::NoRegister, MachineInstr::FrameSetup); in emitPrologue()
422 unsigned ScratchRegister = ARM::NoRegister; in emitPrologue()
521 NumBytes - ArgRegsSaveSize, ARM::NoRegister, in emitEpilogue()
563 unsigned ScratchRegister = ARM::NoRegister; in emitEpilogue()
773 ArgRegsSaveSize + 4, ARM::NoRegister, in emitPopSpecialFixUp()
820 ARM::NoRegister, MachineInstr::FrameDestroy); in emitPopSpecialFixUp()
/openbsd-src/gnu/llvm/llvm/lib/Target/VE/
H A DLVLGen.cpp57 return VE::NoRegister; in getVL()
78 if (Reg != VE::NoRegister) { in runOnMachineBasicBlock()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DRegister.h121 assert(Reg == MCRegister::NoRegister || in asMCReg()
126 bool isValid() const { return Reg != MCRegister::NoRegister; } in isValid()
H A DLiveRegMatrix.h141 MCRegister PhysReg = MCRegister::NoRegister);
H A DRegisterClassInfo.h121 return MCRegister::NoRegister; in getLastCalleeSavedAlias()
/openbsd-src/gnu/llvm/llvm/lib/Target/VE/Disassembler/
H A DVEDisassembler.cpp118 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
119 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
121 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
170 unsigned Reg = VE::NoRegister; in DecodeV64RegisterClass()
207 if (Reg == VE::NoRegister) in DecodeMISCRegisterClass()
/openbsd-src/gnu/llvm/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp136 VE::USRCC, VE::PSW, VE::SAR, VE::NoRegister,
137 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
139 VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
687 if (regIdx > 31 || MISCRegs[regIdx] == VE::NoRegister) in MorphToMISCReg()
816 if (RegNum == VE::NoRegister) { in parseRegisterName()
843 if (RegNo == VE::NoRegister) in tryParseRegister()
846 if (RegNo != VE::NoRegister) { in tryParseRegister()
1356 Operands.push_back(BaseReg != VE::NoRegister in parseMEMAsOperand()
1362 if (BaseReg != VE::NoRegister) in parseMEMAsOperand()
1388 Operands.push_back(BaseReg != VE::NoRegister in parseMEMAsOperand()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp505 assert(Producer != Hexagon::NoRegister); in getSingleInstruction()
520 assert(Producer != Hexagon::NoRegister); in getSingleInstruction()
686 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); in DecodeCtrRegsRegisterClass()
687 if (CtrlRegDecoderTable[RegNo] == NoRegister) in DecodeCtrRegsRegisterClass()
714 static_assert(NoRegister == 0, "Expecting NoRegister to be 0"); in DecodeCtrRegs64RegisterClass()
715 if (CtrlReg64DecoderTable[RegNo] == NoRegister) in DecodeCtrRegs64RegisterClass()
813 if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister) in DecodeSysRegsRegisterClass()
841 if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister) in DecodeSysRegs64RegisterClass()
867 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister) in DecodeGuestRegsRegisterClass()
894 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister) in DecodeGuestRegs64RegisterClass()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp320 if (!((Base.isReg() && Base.getReg() != X86::NoRegister) || Base.isFI())) in isRelevantAddressingMode()
326 if (!(Index.isReg() && Index.getReg() == X86::NoRegister)) in isRelevantAddressingMode()
328 if (!(Segment.isReg() && Segment.getReg() == X86::NoRegister)) in isRelevantAddressingMode()
398 .addReg(X86::NoRegister) in buildCopy()
400 .addReg(X86::NoRegister) in buildCopy()
417 .addReg(X86::NoRegister) in buildCopy()
419 .addReg(X86::NoRegister) in buildCopy()
H A DX86LoadValueInjectionRetHardening.cpp83 if (ClobberReg != X86::NoRegister) { in runOnMachineFunction()
H A DX86FixupGadgets.cpp398 return X86::NoRegister; // Non-GP Reg in getWidestRegForReg()
627 if (SwapReg1 == X86::NoRegister || SwapReg2 == X86::NoRegister || in fixupInstruction()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCTLSDynamicCall.cpp82 Register InReg = PPC::NoRegister; in processBlock()
152 assert(InReg != PPC::NoRegister && "Operand must be a register"); in processBlock()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp37 HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
94 unsigned PredReg = Hexagon::NoRegister; in init()
136 unsigned R = MCI.getOperand(i).getReg(), S = Hexagon::NoRegister; in init()
457 if (ProducerPredInfo.Register != Hexagon::NoRegister && in checkNewValues()
577 (ProducerPredicate.Register == Hexagon::NoRegister || in registerProducer()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2133 if (expandLoadAddress(Mips::T9, Mips::NoRegister, Inst.getOperand(0), in processInstruction()
2397 return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister, in tryExpandInstruction()
2734 if (SrcReg != Mips::NoRegister) in loadImmediate()
2841 if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false, in loadImmediate()
2878 if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister, in expandLoadImm()
2922 bool UseSrcReg = SrcReg != Mips::NoRegister && SrcReg != Mips::ZERO && in loadAndAddSymbolAddress()
3412 return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc, in expandLoadSingleImmToGPR()
3439 if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, Mips::NoRegister, in expandLoadSingleImmToFPR()
3485 if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false, in expandLoadDoubleImmToGPR()
3489 if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false, in expandLoadDoubleImmToGPR()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DInterferenceCache.h105 PhysReg = MCRegister::NoRegister; in clear()
/openbsd-src/gnu/llvm/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp95 RegNum = (RegLoNum != AVR::NoRegister) ? RegLoNum : RegNum; in getPrettyRegisterName()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp170 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { in initLLVMToSEHAndCVRegMapping()
748 default: return X86::NoRegister; in getX86SubSuperRegisterOrZero()
772 default: return X86::NoRegister; in getX86SubSuperRegisterOrZero()
809 default: return X86::NoRegister; in getX86SubSuperRegisterOrZero()
845 default: return X86::NoRegister; in getX86SubSuperRegisterOrZero()
920 assert(Res != X86::NoRegister && "Unexpected register or VT"); in getX86SubSuperRegister()

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