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Searched refs:NewOpcode (Results 1 – 25 of 46) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp85 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
88 NewOpcode = Hexagon::J2_jumpf; in InvertAndChangeJumpTarget()
91 NewOpcode = Hexagon::J2_jumpt; in InvertAndChangeJumpTarget()
94 NewOpcode = Hexagon::J2_jumpfnewpt; in InvertAndChangeJumpTarget()
97 NewOpcode = Hexagon::J2_jumptnewpt; in InvertAndChangeJumpTarget()
103 MI.setDesc(TII->get(NewOpcode)); in InvertAndChangeJumpTarget()
H A DHexagonVLIWPacketizer.cpp461 int NewOpcode; in promoteToDotNew() local
463 NewOpcode = HII->getDotNewPredOp(MI, MBPI); in promoteToDotNew()
465 NewOpcode = HII->getDotNewOp(MI); in promoteToDotNew()
466 MI.setDesc(HII->get(NewOpcode)); in promoteToDotNew()
471 int NewOpcode = HII->getDotOldOp(MI); in demoteToDotOld() local
472 MI.setDesc(HII->get(NewOpcode)); in demoteToDotOld()
890 int NewOpcode = (RC != &Hexagon::PredRegsRegClass) ? HII->getDotNewOp(MI) : in canPromoteToDotNew() local
892 const MCInstrDesc &D = HII->get(NewOpcode); in canPromoteToDotNew()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DMVEVPTBlockPass.cpp68 unsigned &NewOpcode) { in findVCMPToFoldIntoVPST() argument
83 NewOpcode = VCMPOpcodeToVPT(CmpMI->getOpcode()); in findVCMPToFoldIntoVPST()
84 if (NewOpcode == 0) in findVCMPToFoldIntoVPST()
275 unsigned NewOpcode; in InsertVPTBlocks() local
277 if (MachineInstr *VCMP = findVCMPToFoldIntoVPST(MI, TRI, NewOpcode)) { in InsertVPTBlocks()
279 MIBuilder = BuildMI(Block, MI, DL, TII->get(NewOpcode)); in InsertVPTBlocks()
/openbsd-src/gnu/llvm/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp137 int NewOpcode; in InsertSPImmInst() local
139 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in InsertSPImmInst()
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
145 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in InsertSPImmInst()
146 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
152 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in InsertSPImmInst()
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DSIShrinkInstructions.cpp359 unsigned NewOpcode = AMDGPU::getMIMGOpcode(Info->BaseOpcode, NewEncoding, in shrinkMIMG() local
361 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
395 unsigned NewOpcode = AMDGPU::INSTRUCTION_LIST_END; in shrinkMadFma() local
412 NewOpcode = AMDGPU::V_MADAK_F32; in shrinkMadFma()
415 NewOpcode = AMDGPU::V_FMAAK_F32; in shrinkMadFma()
418 NewOpcode = AMDGPU::V_MADAK_F16; in shrinkMadFma()
422 NewOpcode = ST->hasTrue16BitInsts() ? AMDGPU::V_FMAAK_F16_t16 in shrinkMadFma()
441 NewOpcode = AMDGPU::V_MADMK_F32; in shrinkMadFma()
444 NewOpcode = AMDGPU::V_FMAMK_F32; in shrinkMadFma()
447 NewOpcode = AMDGPU::V_MADMK_F16; in shrinkMadFma()
[all …]
H A DGCNCreateVOPD.cpp66 int NewOpcode = AMDGPU::getVOPDFull(AMDGPU::getVOPDOpcode(Opc1), in doReplace() local
68 assert(NewOpcode != -1 && in doReplace()
72 FirstMI->getDebugLoc(), SII->get(NewOpcode)) in doReplace()
H A DR600MachineCFGStructurizer.cpp200 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
202 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
204 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
205 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
208 MachineBasicBlock::iterator I, int NewOpcode,
435 int NewOpcode, const DebugLoc &DL) { in insertInstrEnd() argument
437 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
444 int NewOpcode, in insertInstrBefore() argument
447 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
457 MachineBasicBlock::iterator I, int NewOpcode) { in insertInstrBefore() argument
[all …]
H A DSIWholeQuadMode.cpp771 unsigned NewOpcode = 0; in splitBlock() local
774 NewOpcode = AMDGPU::S_AND_B32_term; in splitBlock()
777 NewOpcode = AMDGPU::S_AND_B64_term; in splitBlock()
780 NewOpcode = AMDGPU::S_MOV_B32_term; in splitBlock()
783 NewOpcode = AMDGPU::S_MOV_B64_term; in splitBlock()
788 if (NewOpcode) in splitBlock()
789 TermMI->setDesc(TII->get(NewOpcode)); in splitBlock()
H A DSIOptimizeExecMasking.cpp558 const int NewOpcode = AMDGPU::getVCMPXOpFromVCMP(VCmp.getOpcode()); in optimizeVCMPSaveExecSequence() local
560 if (NewOpcode == -1) in optimizeVCMPSaveExecSequence()
580 VCmp.getDebugLoc(), TII->get(NewOpcode)); in optimizeVCMPSaveExecSequence()
H A DSIISelLowering.h79 unsigned NewOpcode) const;
81 unsigned NewOpcode) const;
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp531 unsigned NewOpcode = AluI->getOpcode(); in optLEAALU() local
532 NewMI1 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode), in optLEAALU()
537 NewMI2 = BuildMI(MBB, InsertPos, AluI->getDebugLoc(), TII->get(NewOpcode), in optLEAALU()
595 unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode()); in optTwoAddrLEA() local
601 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
606 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
619 unsigned NewOpcode = getINCDECFromLEA(MI.getOpcode(), IsINC); in optTwoAddrLEA() local
623 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
626 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
630 unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp); in optTwoAddrLEA() local
[all …]
H A DX86MCInstLower.cpp349 unsigned NewOpcode = 0; in SimplifyMOVSX() local
356 NewOpcode = X86::CBW; in SimplifyMOVSX()
360 NewOpcode = X86::CWDE; in SimplifyMOVSX()
364 NewOpcode = X86::CDQE; in SimplifyMOVSX()
368 if (NewOpcode != 0) { in SimplifyMOVSX()
370 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
/openbsd-src/gnu/llvm/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp111 void changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode,
264 int NewOpcode = ARC::getPostIncOpcode(Ldst.getOpcode()); in tryToCombine() local
265 assert(NewOpcode > 0 && "No postincrement form found"); in tryToCombine()
267 changeToAddrMode(Ldst, NewOpcode, NewBaseReg, Add.getOperand(2)); in tryToCombine()
452 void ARCOptAddrMode::changeToAddrMode(MachineInstr &Ldst, unsigned NewOpcode, in changeToAddrMode() argument
470 Ldst.setDesc(AST->getInstrInfo()->get(NewOpcode)); in changeToAddrMode()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp191 int NewOpcode = -1; in encodeInstruction() local
194 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
195 if (NewOpcode == -1) in encodeInstruction()
196 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
199 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); in encodeInstruction()
202 if (NewOpcode == -1) in encodeInstruction()
203 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); in encodeInstruction()
205 if (NewOpcode != -1) { in encodeInstruction()
209 TmpInst.setOpcode (NewOpcode); in encodeInstruction()
/openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.cpp228 unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode()); in eliminateFrameIndex() local
233 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode), in eliminateFrameIndex()
/openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp69 unsigned NewOpcode) const { in splitMove()
110 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
111 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
130 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc() local
131 assert(NewOpcode && "No support for huge argument lists yet"); in splitAdjDynAlloc()
132 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
967 unsigned NewOpcode; in convertToThreeAddress() local
969 NewOpcode = SystemZ::RISBG; in convertToThreeAddress()
972 NewOpcode = SystemZ::RISBGN; in convertToThreeAddress()
974 NewOpcode = SystemZ::RISBMux; in convertToThreeAddress()
[all …]
H A DSystemZFrameLowering.cpp726 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue() local
730 if (!NewOpcode) { in emitEpilogue()
735 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
736 assert(NewOpcode && "No restore instruction available"); in emitEpilogue()
739 MBBI->setDesc(ZII->get(NewOpcode)); in emitEpilogue()
H A DSystemZInstrInfo.h178 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp1592 std::string NewOpcode; in ParseInstruction() local
1594 NewOpcode = std::string(Name); in ParseInstruction()
1595 NewOpcode += '+'; in ParseInstruction()
1596 Name = NewOpcode; in ParseInstruction()
1599 NewOpcode = std::string(Name); in ParseInstruction()
1600 NewOpcode += '-'; in ParseInstruction()
1601 Name = NewOpcode; in ParseInstruction()
1607 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
1615 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp516 int NewOpcode; in expand_DestructiveOp() local
518 if ((NewOpcode = AArch64::getSVERevInstr(Opcode)) != -1) in expand_DestructiveOp()
519 Opcode = NewOpcode; in expand_DestructiveOp()
521 else if ((NewOpcode = AArch64::getSVENonRevInstr(Opcode)) != -1) in expand_DestructiveOp()
522 Opcode = NewOpcode; in expand_DestructiveOp()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp1734 unsigned NewOpcode = 0u; in eliminateFrameIndex() local
1782 NewOpcode = ImmToIdxMap.find(OpC)->second; in eliminateFrameIndex()
1783 MI.setDesc(TII.get(NewOpcode)); in eliminateFrameIndex()
1802 if (NewOpcode == PPC::LQX_PSEUDO || NewOpcode == PPC::STQX_PSEUDO) { in eliminateFrameIndex()
1808 MI.setDesc(TII.get(NewOpcode == PPC::LQX_PSEUDO ? PPC::LQ : PPC::STQ)); in eliminateFrameIndex()
H A DPPCISelDAGToDAG.cpp7208 unsigned NewOpcode; in PeepholePPC64ZExt() local
7212 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break; in PeepholePPC64ZExt()
7213 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break; in PeepholePPC64ZExt()
7214 case PPC::SLW: NewOpcode = PPC::SLW8; break; in PeepholePPC64ZExt()
7215 case PPC::SRW: NewOpcode = PPC::SRW8; break; in PeepholePPC64ZExt()
7216 case PPC::LI: NewOpcode = PPC::LI8; break; in PeepholePPC64ZExt()
7217 case PPC::LIS: NewOpcode = PPC::LIS8; break; in PeepholePPC64ZExt()
7218 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break; in PeepholePPC64ZExt()
7219 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break; in PeepholePPC64ZExt()
7220 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break; in PeepholePPC64ZExt()
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp563 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); in replaceWithCompactBranch() local
564 Branch = TII->genInstrWithNewOpc(NewOpcode, Branch); in replaceWithCompactBranch()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h847 int64_t NewOpcode = MatchTable[CurrentIdx++]; in executeMatchTable() local
853 OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode)); in executeMatchTable()
857 << NewOpcode << ")\n"); in executeMatchTable()
/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp951 int NewOpcode = in convertMIMGInst() local
953 if (NewOpcode == -1) in convertMIMGInst()
959 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; in convertMIMGInst()
982 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddr0Idx].RegClass; in convertMIMGInst()
989 MI.setOpcode(NewOpcode); in convertMIMGInst()

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