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Searched refs:MVT (Results 1 – 25 of 278) sorted by relevance

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/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp241 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty); in getArithmeticInstrCost()
247 LT.second.getScalarType() == MVT::i32) { in getArithmeticInstrCost()
273 MVT::getVectorVT(MVT::i16, 2 * LT.second.getVectorNumElements()); in getArithmeticInstrCost()
279 if (ST->useSLMArithCosts() && LT.second == MVT::v4i32) { in getArithmeticInstrCost()
340 { ISD::SHL, MVT::v16i8, { 1, 7, 2, 3 } }, // psllw + pand. in getArithmeticInstrCost()
341 { ISD::SRL, MVT::v16i8, { 1, 7, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
342 { ISD::SRA, MVT::v16i8, { 1, 8, 4, 5 } }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
343 { ISD::SHL, MVT::v32i8, { 1, 8, 2, 3 } }, // psllw + pand. in getArithmeticInstrCost()
344 { ISD::SRL, MVT::v32i8, { 1, 8, 2, 3 } }, // psrlw + pand. in getArithmeticInstrCost()
345 { ISD::SRA, MVT::v32i8, { 1, 9, 4, 5 } }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
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H A DX86ISelLowering.cpp111 MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0)); in X86TargetLowering()
178 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering()
179 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering()
180 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering()
182 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering()
184 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering()
185 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
188 setTruncStoreAction(MVT::i64, MVT::i32, Expand); in X86TargetLowering()
189 setTruncStoreAction(MVT::i64, MVT::i16, Expand); in X86TargetLowering()
190 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); in X86TargetLowering()
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/openbsd-src/gnu/llvm/llvm/include/llvm/Support/
H A DMachineValueType.h31 class MVT {
343 constexpr MVT() = default;
344 constexpr MVT(SimpleValueType SVT) : SimpleTy(SVT) {} in MVT() function
346 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
347 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
348 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
349 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
350 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
351 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
355 return (SimpleTy >= MVT::FIRST_VALUETYPE && in isValid()
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/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp35 InstructionCost RISCVTTIImpl::getLMULCost(MVT VT) { in getLMULCost()
245 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Tp); in getSpliceCost()
259 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Tp); in getShuffleCost()
289 std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Tp); in getShuffleCost()
371 {Intrinsic::floor, MVT::v2f32, 9},
372 {Intrinsic::floor, MVT::v4f32, 9},
373 {Intrinsic::floor, MVT::v8f32, 9},
374 {Intrinsic::floor, MVT::v16f32, 9},
375 {Intrinsic::floor, MVT::nxv1f32, 9},
376 {Intrinsic::floor, MVT::nxv2f32, 9},
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/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DValueTypes.cpp164 case MVT::bf16: return "bf16"; in getEVTString()
165 case MVT::ppcf128: return "ppcf128"; in getEVTString()
166 case MVT::isVoid: return "isVoid"; in getEVTString()
167 case MVT::Other: return "ch"; in getEVTString()
168 case MVT::Glue: return "glue"; in getEVTString()
169 case MVT::x86mmx: return "x86mmx"; in getEVTString()
170 case MVT::x86amx: return "x86amx"; in getEVTString()
171 case MVT::i64x8: return "i64x8"; in getEVTString()
172 case MVT::Metadata: return "Metadata"; in getEVTString()
173 case MVT::Untyped: return "Untyped"; in getEVTString()
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H A DTargetLoweringBase.cpp223 VT == MVT::f32 ? Call_F32 : in getFPLibCall()
224 VT == MVT::f64 ? Call_F64 : in getFPLibCall()
225 VT == MVT::f80 ? Call_F80 : in getFPLibCall()
226 VT == MVT::f128 ? Call_F128 : in getFPLibCall()
227 VT == MVT::ppcf128 ? Call_PPCF128 : in getFPLibCall()
234 if (OpVT == MVT::f16) { in getFPEXT()
235 if (RetVT == MVT::f32) in getFPEXT()
237 if (RetVT == MVT::f64) in getFPEXT()
239 if (RetVT == MVT::f80) in getFPEXT()
241 if (RetVT == MVT::f128) in getFPEXT()
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/openbsd-src/gnu/llvm/llvm/utils/TableGen/
H A DCodeGenTarget.cpp42 MVT::SimpleValueType llvm::getValueType(Record *Rec) { in getValueType()
43 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); in getValueType()
46 StringRef llvm::getName(MVT::SimpleValueType T) { in getName()
48 case MVT::Other: return "UNKNOWN"; in getName()
49 case MVT::iPTR: return "TLI.getPointerTy()"; in getName()
50 case MVT::iPTRAny: return "TLI.getPointerTy()"; in getName()
55 StringRef llvm::getEnumName(MVT::SimpleValueType T) { in getEnumName()
58 case MVT::Other: return "MVT::Other"; in getEnumName()
59 case MVT::i1: return "MVT::i1"; in getEnumName()
60 case MVT::i2: return "MVT::i2"; in getEnumName()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp333 static const auto ValidMinMaxTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
334 MVT::v8i16, MVT::v2i32, MVT::v4i32}; in getIntrinsicInstrCost()
337 if (LT.second == MVT::v2i64) in getIntrinsicInstrCost()
339 if (any_of(ValidMinMaxTys, [&LT](MVT M) { return M == LT.second; })) in getIntrinsicInstrCost()
347 static const auto ValidSatTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
348 MVT::v8i16, MVT::v2i32, MVT::v4i32, in getIntrinsicInstrCost()
349 MVT::v2i64}; in getIntrinsicInstrCost()
355 if (any_of(ValidSatTys, [&LT](MVT M) { return M == LT.second; })) in getIntrinsicInstrCost()
360 static const auto ValidAbsTys = {MVT::v8i8, MVT::v16i8, MVT::v4i16, in getIntrinsicInstrCost()
361 MVT::v8i16, MVT::v2i32, MVT::v4i32, in getIntrinsicInstrCost()
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H A DAArch64ISelDAGToDAG.cpp149 OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i64); in SelectAddrModeIndexedUImm()
206 Res2 = CurDAG->getTargetConstant(ShtAmt, SDLoc(N), MVT::i32); in SelectRoundingVLShr()
246 template<MVT::SimpleValueType VT>
251 template <MVT::SimpleValueType VT>
256 template <MVT::SimpleValueType VT, bool Invert = false>
261 template <MVT::SimpleValueType VT>
296 Imm = CurDAG->getTargetConstant(MulImm, SDLoc(N), MVT::i32); in SelectCntImm()
312 Imm = CurDAG->getTargetConstant(MulImm, SDLoc(N), MVT::i32); in SelectEXTImm()
322 Imm = CurDAG->getRegister(BaseReg + C, MVT::Other); in ImmToTile()
436 bool SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm, SDValue &Shift);
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H A DAArch64CallingConvention.h19 bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
22 bool CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
25 bool CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
28 bool CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
31 bool CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
34 bool CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT, MVT LocVT,
37 bool CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT,
40 bool CC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, MVT LocVT,
43 bool CC_AArch64_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
46 bool RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
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H A DAArch64FastISel.cpp183 bool isTypeLegal(Type *Ty, MVT &VT);
184 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
188 bool simplifyAddress(Address &Addr, MVT VT);
197 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
202 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
205 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
208 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
211 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
215 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
223 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
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/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp488 return (EltVT == MVT::f32 && ST->hasVFP2Base()) || in getCastInstrCost()
489 (EltVT == MVT::f64 && ST->hasFP64()) || in getCastInstrCost()
490 (EltVT == MVT::f16 && ST->hasFullFP16()); in getCastInstrCost()
517 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
518 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
519 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
520 {ISD::ZERO_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
521 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
522 {ISD::ZERO_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
523 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1}, in getCastInstrCost()
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H A DARMCallingConv.h20 bool CC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
23 bool CC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT,
26 bool CC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
29 bool CC_ARM_APCS_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
32 bool FastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
35 bool CC_ARM_Win32_CFGuard_Check(unsigned ValNo, MVT ValVT, MVT LocVT,
38 bool RetCC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT,
41 bool RetCC_ARM_AAPCS_VFP(unsigned ValNo, MVT ValVT, MVT LocVT,
44 bool RetCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
47 bool RetFastCC_ARM_APCS(unsigned ValNo, MVT ValVT, MVT LocVT,
H A DARMCallingConv.cpp21 static bool f64AssignAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, in f64AssignAPCS()
49 static bool CC_ARM_APCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT, in CC_ARM_APCS_Custom_f64()
55 if (LocVT == MVT::v2f64 && in CC_ARM_APCS_Custom_f64()
62 static bool f64AssignAAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, in f64AssignAAPCS()
102 static bool CC_ARM_AAPCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT, in CC_ARM_AAPCS_Custom_f64()
108 if (LocVT == MVT::v2f64 && in CC_ARM_AAPCS_Custom_f64()
114 static bool f64RetAssign(unsigned ValNo, MVT ValVT, MVT LocVT, in f64RetAssign()
134 static bool RetCC_ARM_APCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT, in RetCC_ARM_APCS_Custom_f64()
140 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) in RetCC_ARM_APCS_Custom_f64()
145 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned ValNo, MVT ValVT, MVT LocVT, in RetCC_ARM_AAPCS_Custom_f64()
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp45 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentMemType()
63 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
64 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
66 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
67 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
69 setOperationAction(ISD::LOAD, MVT::v3f32, Promote); in AMDGPUTargetLowering()
70 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
72 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
73 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
75 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
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H A DR600ISelLowering.cpp33 addRegisterClass(MVT::f32, &R600::R600_Reg32RegClass); in R600TargetLowering()
34 addRegisterClass(MVT::i32, &R600::R600_Reg32RegClass); in R600TargetLowering()
35 addRegisterClass(MVT::v2f32, &R600::R600_Reg64RegClass); in R600TargetLowering()
36 addRegisterClass(MVT::v2i32, &R600::R600_Reg64RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::v4f32, &R600::R600_Reg128RegClass); in R600TargetLowering()
38 addRegisterClass(MVT::v4i32, &R600::R600_Reg128RegClass); in R600TargetLowering()
46 setOperationAction(ISD::LOAD, {MVT::i32, MVT::v2i32, MVT::v4i32}, Custom); in R600TargetLowering()
51 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering()
52 setLoadExtAction(Op, VT, MVT::i1, Promote); in R600TargetLowering()
53 setLoadExtAction(Op, VT, MVT::i8, Custom); in R600TargetLowering()
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/openbsd-src/gnu/llvm/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp85 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in ExpandMI()
87 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i8); in ExpandMI()
89 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16); in ExpandMI()
92 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in ExpandMI()
94 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i8); in ExpandMI()
96 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16); in ExpandMI()
99 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i16, MVT::i8); in ExpandMI()
101 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i8); in ExpandMI()
103 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i16); in ExpandMI()
106 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dj), MVT::i16, in ExpandMI()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp34 static const MVT LegalV64[] = { MVT::v64i8, MVT::v32i16, MVT::v16i32 };
35 static const MVT LegalW64[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
36 static const MVT LegalV128[] = { MVT::v128i8, MVT::v64i16, MVT::v32i32 };
37 static const MVT LegalW128[] = { MVT::v256i8, MVT::v128i16, MVT::v64i32 };
39 static std::tuple<unsigned, unsigned, unsigned> getIEEEProperties(MVT Ty) { in getIEEEProperties()
41 MVT ElemTy = Ty.getScalarType(); in getIEEEProperties()
43 case MVT::f16: in getIEEEProperties()
45 case MVT::f32: in getIEEEProperties()
47 case MVT::f64: in getIEEEProperties()
58 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass); in initializeHVXLowering()
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H A DHexagonISelLowering.cpp140 static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, in CC_SkipOdd()
177 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
260 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps); in LowerReturn()
368 if (RVLocs[i].getValVT() == MVT::i1) { in LowerCallResult()
376 MVT::i32, Glue); in LowerCallResult()
385 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); in LowerCallResult()
423 Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32); in LowerCall()
500 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr); in LowerCall()
533 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall()
583 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp42 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_SRet()
43 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_SRet()
55 static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Split_64()
56 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Split_64()
81 static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Ret_Split_64()
82 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Ret_Split_64()
105 static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT, in Analyze_CC_Sparc64_Full()
106 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in Analyze_CC_Sparc64_Full()
108 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in Analyze_CC_Sparc64_Full()
113 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in Analyze_CC_Sparc64_Full()
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/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp119 MVT::SimpleValueType getSimpleType(Type *Ty) { in getSimpleType()
122 : MVT::INVALID_SIMPLE_VALUE_TYPE; in getSimpleType()
124 MVT::SimpleValueType getLegalType(MVT::SimpleValueType VT) { in getLegalType()
126 case MVT::i1: in getLegalType()
127 case MVT::i8: in getLegalType()
128 case MVT::i16: in getLegalType()
129 return MVT::i32; in getLegalType()
130 case MVT::i32: in getLegalType()
131 case MVT::i64: in getLegalType()
132 case MVT::f32: in getLegalType()
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H A DWebAssemblyISelLowering.cpp48 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32; in WebAssemblyTargetLowering()
60 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass); in WebAssemblyTargetLowering()
61 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass); in WebAssemblyTargetLowering()
62 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass); in WebAssemblyTargetLowering()
63 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass); in WebAssemblyTargetLowering()
65 addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
66 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
67 addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
68 addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
69 addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass); in WebAssemblyTargetLowering()
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/openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp59 MVT WebAssembly::parseMVT(StringRef Type) { in parseMVT()
60 return StringSwitch<MVT>(Type) in parseMVT()
61 .Case("i32", MVT::i32) in parseMVT()
62 .Case("i64", MVT::i64) in parseMVT()
63 .Case("f32", MVT::f32) in parseMVT()
64 .Case("f64", MVT::f64) in parseMVT()
65 .Case("i64", MVT::i64) in parseMVT()
66 .Case("v16i8", MVT::v16i8) in parseMVT()
67 .Case("v8i16", MVT::v8i16) in parseMVT()
68 .Case("v4i32", MVT::v4i32) in parseMVT()
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/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp167 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
170 addRegisterClass(MVT::f32, &PPC::GPRCRegClass); in PPCTargetLowering()
173 addRegisterClass(MVT::f64, &PPC::SPERCRegClass); in PPCTargetLowering()
175 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
176 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
181 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in PPCTargetLowering()
182 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in PPCTargetLowering()
185 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); in PPCTargetLowering()
188 setOperationAction(ISD::INLINEASM, MVT::Other, Custom); in PPCTargetLowering()
189 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom); in PPCTargetLowering()
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H A DPPCFastISel.cpp111 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
140 bool isTypeLegal(Type *Ty, MVT &VT);
141 bool isLoadTypeLegal(Type *Ty, MVT &VT);
160 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
163 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
167 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
169 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
170 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
171 unsigned PPCMaterializeInt(const ConstantInt *CI, MVT VT,
177 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
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