Home
last modified time | relevance | path

Searched refs:IssueWidth (Results 1 – 25 of 92) sorted by relevance

1234

/openbsd-src/gnu/llvm/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp73 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer()
105 if (IssueWidth == 0) in atIssueLimit()
108 return IssueCount == IssueWidth; in atIssueLimit()
H A DTargetSchedule.cpp55 ResourceLCM = SchedModel.IssueWidth; in init()
61 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth; in init()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/
H A DMachinePipeliner.h469 int IssueWidth; variable
499 IssueWidth(SM.IssueWidth) { in ResourceManager()
501 if (IssueWidth <= 0) in ResourceManager()
503 IssueWidth = 100; in ResourceManager()
505 IssueWidth = SwpForceIssueWidth; in ResourceManager()
H A DScoreboardHazardRecognizer.h99 unsigned IssueWidth = 0; variable
H A DTargetSchedule.h98 unsigned getIssueWidth() const { return SchedModel.IssueWidth; } in getIssueWidth()
/openbsd-src/gnu/llvm/llvm/lib/MC/
H A DMCSchedule.cpp107 return ((double)SCDesc.NumMicroOps) / SM.IssueWidth; in getReciprocalThroughput()
120 return 1.0 / IssueWidth; in getReciprocalThroughput()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp221 unsigned IssueWidth = TSM.getIssueWidth(); in addPadding() local
223 for (unsigned i = 0, e = IssueWidth * NOOPsToAdd; i != e; ++i) in addPadding()
/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonScheduleV73.td30 let IssueWidth = 4;
H A DHexagonScheduleV69.td31 let IssueWidth = 4;
H A DHexagonScheduleV71.td30 let IssueWidth = 4;
H A DHexagonScheduleV62.td28 let IssueWidth = 4;
H A DHexagonScheduleV68.td30 let IssueWidth = 4;
H A DHexagonScheduleV66.td31 let IssueWidth = 4;
H A DHexagonScheduleV5.td37 let IssueWidth = 4;
H A DHexagonScheduleV65.td31 let IssueWidth = 4;
H A DHexagonScheduleV55.td39 let IssueWidth = 4;
H A DHexagonScheduleV67.td31 let IssueWidth = 4;
H A DHexagonScheduleV71T.td51 let IssueWidth = 3;
H A DHexagonScheduleV67T.td53 let IssueWidth = 3;
H A DHexagonScheduleV60.td72 let IssueWidth = 4;
/openbsd-src/gnu/llvm/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td39 let IssueWidth = 1;
/openbsd-src/gnu/llvm/llvm/tools/llvm-mca/Views/
H A DSummaryView.cpp27 : SM(Model), Source(S), DispatchWidth(Width ? Width : Model.IssueWidth), in SummaryView()
/openbsd-src/gnu/llvm/llvm/include/llvm/MC/
H A DMCSchedule.h256 unsigned IssueWidth; member
/openbsd-src/gnu/llvm/llvm/lib/MCA/Stages/
H A DDispatchStage.cpp35 DispatchWidth = Subtarget.getSchedModel().IssueWidth; in DispatchStage()
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCScheduleA2.td159 let IssueWidth = 1; // 1 instruction is dispatched per cycle.

1234