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Searched refs:IntRegs (Results 1 – 21 of 21) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td14 def: Pat<(int_hexagon_A2_abs IntRegs:$src1),
15 (A2_abs IntRegs:$src1)>, Requires<[HasV5]>;
18 def: Pat<(int_hexagon_A2_abssat IntRegs:$src1),
19 (A2_abssat IntRegs:$src1)>, Requires<[HasV5]>;
20 def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2),
21 (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
22 def: Pat<(int_hexagon_A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2),
23 (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
24 def: Pat<(int_hexagon_A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2),
25 (A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
[all …]
H A DHexagonDepMappings.td11 def A2_negAlias : InstAlias<"$Rd32 = neg($Rs32)", (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32)>;
12 def A2_notAlias : InstAlias<"$Rd32 = not($Rs32)", (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32)>;
13 …fAlias : InstAlias<"if (!$Pu4) $Rd32 = $Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$R…
14 …: InstAlias<"if (!$Pu4.new) $Rd32 = $Rs32", (A2_paddifnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$R…
15 …rtAlias : InstAlias<"if ($Pu4) $Rd32 = $Rs32", (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$R…
16 … : InstAlias<"if ($Pu4.new) $Rd32 = $Rs32", (A2_padditnew IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$R…
19 def A2_zxtbAlias : InstAlias<"$Rd32 = zxtb($Rs32)", (A2_andir IntRegs:$Rd32, IntRegs:$Rs32, 255)>;
20 … : InstAlias<"$Pd4 = cmp.lt($Rs32,$Rt32)", (C2_cmpgt PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>;
21 … InstAlias<"$Pd4 = cmp.ltu($Rs32,$Rt32)", (C2_cmpgtu PredRegs:$Pd4, IntRegs:$Rt32, IntRegs:$Rs32)>;
24 …rf_nopred_mapAlias : InstAlias<"if (!$Pu4) jumpr $Rs32", (J2_jumprf PredRegs:$Pu4, IntRegs:$Rs32)>;
[all …]
H A DHexagonIntrinsics.td23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
24 (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
25 def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, timm:$s16),
26 (A2_addi IntRegs:$Rs, imm:$s16)>;
30 def: Pat<(int_hexagon_A2_sub IntRegs:$Rs, IntRegs:$Rt),
31 (A2_sub IntRegs:$Rs, IntRegs:$Rt)>;
32 def: Pat<(int_hexagon_A2_subri timm:$s10, IntRegs:$Rs),
33 (A2_subri imm:$s10, IntRegs:$Rs)>;
37 def: Pat<(int_hexagon_M2_mpyi IntRegs:$Rs, IntRegs:$Rt),
38 (M2_mpyi IntRegs:$Rs, IntRegs:$Rt)>;
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H A DHexagonDepInstrInfo.td12 (outs IntRegs:$Rd32),
13 (ins IntRegs:$Rs32),
32 (outs IntRegs:$Rd32),
33 (ins IntRegs:$Rs32),
44 (outs IntRegs:$Rd32),
45 (ins IntRegs:$Rs32, IntRegs:$Rt32),
60 (outs IntRegs:$Rd32),
61 (ins IntRegs:$Rt32, IntRegs:$Rs32),
72 (outs IntRegs:$Rd32),
73 (ins IntRegs:$Rt32, IntRegs:$Rs32),
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H A DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
12 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
13 (MI HvxVR:$src1, IntRegs:$src2)>;
47 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
48 (MI HvxWR:$src1, IntRegs:$src2)>;
49 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, IntRegs:$src2),
50 (MI HvxWR:$src1, IntRegs:$src2)>;
54 def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
55 (MI HvxWR:$src1, HvxWR:$src2, IntRegs:$src3)>;
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H A DHexagonIntrinsicsV60.td65 def : Pat <(store (v64i1 HvxQR:$src1), (i32 IntRegs:$addr)),
66 (V6_vS32b_ai IntRegs:$addr, 0,
70 def : Pat <(v64i1 (load (i32 IntRegs:$addr))),
72 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>;
74 def : Pat <(store (v128i1 HvxQR:$src1), (i32 IntRegs:$addr)),
75 (V6_vS32b_ai IntRegs:$addr, 0,
79 def : Pat <(v128i1 (load (i32 IntRegs:$addr))),
81 (v32i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>;
85 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
86 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
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H A DHexagonPatternsV65.td13 (ins IntRegs:$_dst_, s4_0Imm:$Ii,
14 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
23 (ins IntRegs:$_dst_, s4_0Imm:$Ii,
24 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
33 (ins IntRegs:$_dst_, s4_0Imm:$Ii,
34 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
47 (ins IntRegs:$_dst_, s4_0Imm:$Ii,
48 RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
58 (ins IntRegs:$_dst_, s4_0Imm:$Ii,
59 RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
[all …]
H A DHexagonPseudo.td13 def I32 : PatLeaf<(i32 IntRegs:$R)>;
15 def F32 : PatLeaf<(f32 IntRegs:$R)>;
25 def A2_iconst : Pseudo<(outs IntRegs:$Rd32),
44 : InstHexagon<(outs IntRegs:$dst),
65 def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v),
134 : InstHexagon<(outs), (ins b30_2Imm:$offset, IntRegs:$src2),
209 def PS_callr_nr: InstHexagon<(outs), (ins IntRegs:$Rs),
245 : InstHexagon<(outs), (ins IntRegs:$dst), "jumpr $dst", [],
271 def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
282 def PS_fi : Pseudo<(outs IntRegs:$Rd),
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H A DHexagonPatterns.td83 def V4I8: PatLeaf<(v4i8 IntRegs:$R)>;
84 def V2I16: PatLeaf<(v2i16 IntRegs:$R)>;
477 defm: NopCast_pat<i32, v2i16, IntRegs>;
478 defm: NopCast_pat<i32, v4i8, IntRegs>;
479 defm: NopCast_pat<v2i16, v4i8, IntRegs>;
774 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
776 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
778 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
780 (C2_not (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt))>;
949 def IsPosHalf : PatLeaf<(i32 IntRegs:$a), [{
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H A DHexagonIntrinsicsV5.td177 def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2,
179 (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>;
184 IntRegs:$src3, u2_0ImmPred:$src4),
186 IntRegs:$src3, u2_0ImmPred:$src4)>;
H A DHexagonRegisterInfo.td533 def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32,
/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/
H A DSparcInstrAliases.td22 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
27 (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
47 (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
51 (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
70 (movrrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, condVal)>;
74 (movrri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, condVal)>;
168 (TICCrr G0, IntRegs:$rs2, condVal)>,
172 (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
178 (TXCCrr G0, IntRegs:$rs2, condVal)>,
182 (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
[all …]
H A DSparcInstrInfo.td395 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
399 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
437 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$rd), (ins (MEMrr $rs1, $rs2):$addr),
439 def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$rd), (ins (MEMri $rs1, $simm13):$addr),
441 def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$rd),
517 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
538 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
560 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
579 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>;
580 defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
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H A DSparcInstr64Bit.td22 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
200 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
211 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
220 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
246 (outs IntRegs:$rd),
325 def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd),
326 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
330 def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd),
331 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
393 def MOVRrr : F4_4r<0b101111, 0b00000, (outs IntRegs:$rd),
[all …]
H A DSparcRegisterInfo.td331 def IntRegs : RegisterClass<"SP", [i32, i64], 32,
337 // Should be in the same order as IntRegs.
346 // to be a sub-class of IntRegs. That works out because requiring a 64-bit
348 def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>;
H A DSparcInstrFormats.td229 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
/openbsd-src/gnu/llvm/llvm/docs/
H A DHowToUseInstrMappings.rst121 def ADD : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$a, IntRegs:$b),
123 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$a),
124 (i32 IntRegs:$b)))]>;
126 def ADD_Pt : ALU32_rr<(outs IntRegs:$dst),
127 (ins PredRegs:$p, IntRegs:$a, IntRegs:$b),
131 def ADD_Pf : ALU32_rr<(outs IntRegs:$dst),
132 (ins PredRegs:$p, IntRegs:$a, IntRegs:$b),
142 def ADD : PredRel, ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$a, IntRegs:$b),
144 [(set (i32 IntRegs:$dst), (add (i32 IntRegs:$a),
145 (i32 IntRegs:$b)))]> {
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H A DWritingAnLLVMBackend.rst529 ``FPRegs``, ``DFPRegs``, and ``IntRegs``. For all three register classes, the
544 def IntRegs : RegisterClass<"SP", [i32], 32,
571 associated register classes. The order of registers in ``IntRegs`` reflects
572 the order in the definition of ``IntRegs`` in the target description file.
576 // IntRegs Register Class...
577 static const unsigned IntRegs[] = {
596 // IntRegs Sub-register Classes...
601 // IntRegs Super-register Classes..
606 // IntRegs Register Class sub-classes...
611 // IntRegs Register Class super-classes...
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/openbsd-src/gnu/llvm/llvm/lib/MC/
H A DMCWin64EH.cpp820 IntRegs, in tryARM64PackedUnwind() enumerator
855 Location = IntRegs; in tryARM64PackedUnwind()
884 if (Location != IntRegs || Inst.Offset != 8 * RegI || in tryARM64PackedUnwind()
890 if (Location != IntRegs || Inst.Offset != 8 * RegI) in tryARM64PackedUnwind()
902 if (Location != IntRegs || Inst.Offset != 8 * RegI || in tryARM64PackedUnwind()
928 if ((Location != IntRegs && Location != FloatRegs) || in tryARM64PackedUnwind()
936 if (Location == IntRegs) in tryARM64PackedUnwind()
944 if (Location != IntRegs && Location != FloatRegs && Location != InputArgs) in tryARM64PackedUnwind()
951 if (Location != Start2 && Location != Start3 && Location != IntRegs && in tryARM64PackedUnwind()
968 if (Location != Start2 && Location != Start3 && Location != IntRegs && in tryARM64PackedUnwind()
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/openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp144 static const MCPhysReg IntRegs[32] = { variable
1317 RegNo = IntRegs[intVal]; in matchRegisterName()
1324 RegNo = IntRegs[8 + intVal]; in matchRegisterName()
1330 RegNo = IntRegs[16 + intVal]; in matchRegisterName()
1336 RegNo = IntRegs[24 + intVal]; in matchRegisterName()
1360 RegNo = IntRegs[intVal]; in matchRegisterName()
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2870 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; in CC_MipsO32() local
2932 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2936 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2940 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2947 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2949 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2954 MCRegister HiReg = State.AllocateReg(IntRegs); in CC_MipsO32()
2965 State.AllocateReg(IntRegs); in CC_MipsO32()
2969 unsigned Reg2 = State.AllocateReg(IntRegs); in CC_MipsO32()
2971 State.AllocateReg(IntRegs); in CC_MipsO32()
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