| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1293 EVT InVT = InOp.getValueType(); in SplitVecRes_BITCAST() local
1296 switch (getTypeAction(InVT)) { in SplitVecRes_BITCAST()
1578 EVT InVT = Op.getValueType(); in SplitVecRes_StrictFPOp() local
1579 if (InVT.isVector()) { in SplitVecRes_StrictFPOp()
1582 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) in SplitVecRes_StrictFPOp()
2254 EVT InVT = N->getOperand(0).getValueType(); in SplitVecRes_UnaryOp() local
2255 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) in SplitVecRes_UnaryOp()
3037 EVT InVT = Lo.getValueType(); in SplitVecOp_UnaryOp() local
3040 InVT.getVectorElementCount()); in SplitVecOp_UnaryOp()
3650 EVT InVT = InVec->getValueType(0); in SplitVecOp_TruncateHelper() local
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| H A D | LegalizeTypesGeneric.cpp | 44 EVT InVT = InOp.getValueType(); in ExpandRes_BITCAST() local
48 switch (getTypeAction(InVT)) { in ExpandRes_BITCAST()
66 if (TLI.hasBigEndianPartOrdering(InVT, DL) != in ExpandRes_BITCAST()
89 assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); in ExpandRes_BITCAST()
92 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(InVT); in ExpandRes_BITCAST()
102 if (InVT.isVector() && OutVT.isInteger()) { in ExpandRes_BITCAST()
162 Align InAlign = DAG.getReducedAlign(InVT, /*UseABI=*/false); in ExpandRes_BITCAST()
165 SDValue StackPtr = DAG.CreateStackTemporary(InVT.getStoreSize(), Align); in ExpandRes_BITCAST()
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| H A D | LegalizeIntegerTypes.cpp | 386 EVT InVT = InOp.getValueType(); in PromoteIntRes_BITCAST() local
387 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); in PromoteIntRes_BITCAST()
392 switch (getTypeAction(InVT)) { in PromoteIntRes_BITCAST()
454 unsigned ShiftAmt = NInVT.getSizeInBits() - InVT.getSizeInBits(); in PromoteIntRes_BITCAST()
1155 EVT InVT = N->getOperand(OpNo).getValueType(); in PromoteIntRes_SETCC() local
1158 EVT SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
1164 if (getTypeAction(InVT) == TargetLowering::TypePromoteInteger) { in PromoteIntRes_SETCC()
1165 InVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT); in PromoteIntRes_SETCC()
1166 SVT = getSetCCResultType(InVT); in PromoteIntRes_SETCC()
1363 EVT InVT = InOp.getValueType(); in PromoteIntRes_TRUNCATE() local
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| H A D | DAGCombiner.cpp | 21485 EVT InVT = Vec.getValueType(); in reduceBuildVecToShuffle() local
21497 if (InVT.isSimple() && NearestPow2 > 2 && MaxIndex < NearestPow2 && in reduceBuildVecToShuffle()
21501 InVT.getVectorElementType(), SplitSize); in reduceBuildVecToShuffle()
21504 InVT.getVectorNumElements()) { in reduceBuildVecToShuffle()
21688 EVT InVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumElems); in convertBuildVecZextToZext() local
21691 if (LegalTypes && !TLI.isTypeLegal(InVT)) in convertBuildVecZextToZext()
21701 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InVT, In, in convertBuildVecZextToZext()
22960 EVT InVT = V.getValueType(); in visitEXTRACT_SUBVECTOR() local
22962 unsigned EltSize = InVT.getScalarSizeInBits(); in visitEXTRACT_SUBVECTOR()
22966 EVT EltVT = InVT.getVectorElementType(); in visitEXTRACT_SUBVECTOR()
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| H A D | SelectionDAG.cpp | 3520 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3521 APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements()); in computeKnownBits()
3534 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3535 APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements()); in computeKnownBits()
3552 EVT InVT = Op.getOperand(0).getValueType(); in computeKnownBits() local
3553 APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements()); in computeKnownBits()
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| H A D | LegalizeDAG.cpp | 2144 EVT InVT = Node->getOperand(Node->isStrictFPOpcode() ? 1 : 0).getValueType(); in ExpandArgFPLibCall() local
2145 RTLIB::Libcall LC = RTLIB::getFPLibCall(InVT.getSimpleVT(), in ExpandArgFPLibCall()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2369 EVT InVT = N->getOperand(0)->getValueType(0); in performVectorExtendToFPCombine() local
2372 if (ResVT == MVT::v4f32 && (InVT == MVT::v4i16 || InVT == MVT::v4i8)) in performVectorExtendToFPCombine()
2374 else if (ResVT == MVT::v2f64 && (InVT == MVT::v2i16 || InVT == MVT::v2i8)) in performVectorExtendToFPCombine()
2601 EVT InVT = MVT::i16, OutVT = MVT::i8; in truncateVectorWithNARROW() local
2603 InVT = MVT::i32; in truncateVectorWithNARROW()
2607 InVT = EVT::getVectorVT(Ctx, InVT, SubSizeInBits / InVT.getSizeInBits()); in truncateVectorWithNARROW()
2616 Lo = DAG.getBitcast(InVT, Lo); in truncateVectorWithNARROW()
2617 Hi = DAG.getBitcast(InVT, Hi); in truncateVectorWithNARROW()
2637 EVT InVT = In.getValueType(); in performTruncateCombine() local
2638 if (!InVT.isSimple()) in performTruncateCombine()
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| /openbsd-src/gnu/llvm/llvm/utils/TableGen/ |
| H A D | CodeGenDAGPatterns.h | 278 bool MergeInTypeInfo(TypeSetByHwMode &Out, MVT::SimpleValueType InVT) { in MergeInTypeInfo()
279 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); in MergeInTypeInfo()
281 bool MergeInTypeInfo(TypeSetByHwMode &Out, ValueTypeByHwMode InVT) { in MergeInTypeInfo()
282 return MergeInTypeInfo(Out, TypeSetByHwMode(InVT)); in MergeInTypeInfo()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 7044 EVT InVT = In.getValueType(); in getEXTEND_VECTOR_INREG() local
7045 assert(VT.isVector() && InVT.isVector() && "Expected vector VTs."); in getEXTEND_VECTOR_INREG()
7052 if (InVT.getSizeInBits() > 128) { in getEXTEND_VECTOR_INREG()
7053 assert(VT.getSizeInBits() == InVT.getSizeInBits() && in getEXTEND_VECTOR_INREG()
7055 unsigned Scale = VT.getScalarSizeInBits() / InVT.getScalarSizeInBits(); in getEXTEND_VECTOR_INREG()
7058 InVT = In.getValueType(); in getEXTEND_VECTOR_INREG()
7061 if (VT.getVectorNumElements() != InVT.getVectorNumElements()) in getEXTEND_VECTOR_INREG()
22178 MVT InVT = In.getSimpleValueType(); in LowerAVXExtend() local
22182 assert(VT.isVector() && InVT.isVector() && "Expected vector type"); in LowerAVXExtend()
22185 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() && in LowerAVXExtend()
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| H A D | X86InstrAVX512.td | 350 X86VectorVTInfo InVT,
355 !con((ins InVT.RC:$src1), NonTiedIns),
356 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
357 !con((ins InVT.RC:$src1, InVT.KRCWM:$mask), NonTiedIns),
359 (vselect_mask InVT.KRCWM:$mask, RHS,
360 (bitconvert InVT.RC:$src1)),
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3891 EVT InVT = Op.getOperand(IsStrict ? 1 : 0).getValueType(); in LowerVectorFP_TO_INT() local
3903 useSVEForFixedLengthVectorVT(InVT, in LowerVectorFP_TO_INT()
3907 unsigned NumElts = InVT.getVectorNumElements(); in LowerVectorFP_TO_INT()
3910 if (InVT.getVectorElementType() == MVT::f16 && in LowerVectorFP_TO_INT()
3926 uint64_t InVTSize = InVT.getFixedSizeInBits(); in LowerVectorFP_TO_INT()
3930 InVT = InVT.changeVectorElementTypeToInteger(); in LowerVectorFP_TO_INT()
3931 SDValue Cv = DAG.getNode(Op.getOpcode(), dl, {InVT, MVT::Other}, in LowerVectorFP_TO_INT()
3937 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(), in LowerVectorFP_TO_INT()
3962 ISD::EXTRACT_VECTOR_ELT, dl, InVT.getScalarType(), in LowerVectorFP_TO_INT()
4140 EVT InVT = In.getValueType(); in LowerVectorINT_TO_FP() local
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| H A D | SVEInstrFormats.td | 2566 ValueType OutVT, ValueType InVT,
2569 …def : SVE_4_Op_Imm_Pat<OutVT, op, OutVT, InVT, InVT, i32, VectorIndexH32b_timm, !cast<Instruction>…
2601 ValueType InVT, SDPatternOperator op> {
2603 def : SVE_3_Op_Pat<OutVT, op, OutVT, InVT, InVT, !cast<Instruction>(NAME)>;
8340 multiclass sve_float_dot<bit bf, string asm, ValueType InVT, SDPatternOperator op> {
8342 def : SVE_3_Op_Pat<nxv4f32, op, nxv4f32, InVT, InVT, !cast<Instruction>(NAME)>;
8365 multiclass sve_float_dot_indexed<bit bf, string asm, ValueType InVT, SDPatternOperator op> {
8367 …def : SVE_4_Op_Imm_Pat<nxv4f32, op, nxv4f32, InVT, InVT, i32, VectorIndexS32b_timm, !cast<Instruct…
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| H A D | AArch64ISelDAGToDAG.cpp | 4152 EVT InVT = Node->getOperand(0).getValueType(); in Select() local
4153 if (VT.isScalableVector() || InVT.isFixedLengthVector()) in Select()
4176 EVT InVT = Node->getOperand(1).getValueType(); in Select() local
4177 if (VT.isFixedLengthVector() || InVT.isScalableVector()) in Select()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 1749 MVT InVT = V.getSimpleValueType(); in Select() local
1757 if (InVT.isFixedLengthVector()) in Select()
1758 InVT = TLI.getContainerForFixedLengthVector(InVT); in Select()
1764 InVT, SubVecContainerVT, Idx, TRI); in Select()
1775 unsigned InRegClassID = RISCVTargetLowering::getRegClassIDForVecVT(InVT); in Select()
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| H A D | RISCVISelLowering.cpp | 6780 MVT InVT = Op.getOperand(0).getSimpleValueType(); in lowerFixedLengthVectorSetccToRVV() local
6781 MVT ContainerVT = getContainerForFixedLengthVector(InVT); in lowerFixedLengthVectorSetccToRVV()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 3510 EVT InVT = In.getValueType(); in lowerBITCAST() local
3525 if (InVT == MVT::i32 && ResVT == MVT::f32) { in lowerBITCAST()
3541 if (InVT == MVT::f32 && ResVT == MVT::i32) { in lowerBITCAST()
4768 MVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBytes * 8), in getPermuteNode() local
4770 Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0); in getPermuteNode()
4771 Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1); in getPermuteNode()
4775 Op = DAG.getNode(SystemZISD::PERMUTE_DWORDS, DL, InVT, Op0, Op1, Op2); in getPermuteNode()
4781 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1); in getPermuteNode()
5153 EVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBits), in insertUnpackIfPrepared() local
5155 SDValue PackedOp = DAG.getNode(ISD::BITCAST, DL, InVT, Op); in insertUnpackIfPrepared()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 2947 EVT InVT = InputOp.getValueType(); in computeLogicOpInGPR() local
2948 return SDValue(CurDAG->getMachineNode(InVT == MVT::i32 ? PPC::RLDICL_32 : in computeLogicOpInGPR()
2949 PPC::RLDICL, dl, InVT, InputOp, in computeLogicOpInGPR()
3092 EVT InVT = LHS.getValueType(); in getCompoundZeroComparisonInGPR() local
3093 bool Is32Bit = InVT == MVT::i32; in getCompoundZeroComparisonInGPR()
3101 dl, InVT, LHS, LHS), 0); in getCompoundZeroComparisonInGPR()
5625 EVT InVT = N->getOperand(0).getValueType(); in Select() local
5626 assert((InVT == MVT::i64 || InVT == MVT::i32) && in Select()
5629 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDI8_rec : PPC::ANDI_rec; in Select()
5630 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue, in Select()
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| H A D | PPCISelLowering.cpp | 8515 EVT InVT = Src.getValueType(); in LowerINT_TO_FP() local
8518 isOperationCustom(Op.getOpcode(), InVT)) in LowerINT_TO_FP()
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