Searched refs:InLo (Results 1 – 4 of 4) sorted by relevance
| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1525 SDValue InLo, InHi; in SplitVecRes_ExtVecInRegOp() local
1528 GetSplitVector(N0, InLo, InHi); in SplitVecRes_ExtVecInRegOp()
1530 std::tie(InLo, InHi) = DAG.SplitVectorOperand(N, 0); in SplitVecRes_ExtVecInRegOp()
1532 EVT InLoVT = InLo.getValueType(); in SplitVecRes_ExtVecInRegOp()
1551 InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi); in SplitVecRes_ExtVecInRegOp()
1553 Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo); in SplitVecRes_ExtVecInRegOp()
2747 SDValue InLo, InHi; in SplitVecRes_VECTOR_REVERSE() local
2748 GetSplitVector(N->getOperand(0), InLo, InHi); in SplitVecRes_VECTOR_REVERSE()
2752 Hi = DAG.getNode(ISD::VECTOR_REVERSE, DL, InLo.getValueType(), InLo); in SplitVecRes_VECTOR_REVERSE()
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1391 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SubV, V1}); in insertHvxSubvectorReg() local
1393 return DAG.getNode(ISD::SELECT, dl, VecTy, PickHi, InHi, InLo); in insertHvxSubvectorReg()
1438 SDValue InLo = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {SingleV, V1}); in insertHvxSubvectorReg() local
1440 return DAG.getNode(ISD::SELECT, dl, VecTy, PickHi, InHi, InLo); in insertHvxSubvectorReg()
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 1280 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, in initAccumulator() local
1284 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi); in initAccumulator()
|
| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 22651 SDValue InLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i16, In, in LowerTRUNCATE() local
22655 return DAG.getNode(X86ISD::PACKUS, DL, VT, InLo, InHi); in LowerTRUNCATE()
|