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Searched refs:In64BitMode (Results 1 – 25 of 25) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrSNP.td21 Requires<[In64BitMode]>;
26 XD, Requires<[In64BitMode]>;
35 Requires<[In64BitMode]>;
40 Requires<[In64BitMode]>;
43 def : InstAlias<"psmash\t{%rax|rax}", (PSMASH)>, Requires<[In64BitMode]>;
44 def : InstAlias<"pvalidate\t{%rax|rax}", (PVALIDATE64)>, Requires<[In64BitMode]>;
46 def : InstAlias<"rmpupdate\t{%rax|rax}", (RMPUPDATE)>, Requires<[In64BitMode]>;
47 def : InstAlias<"rmpadjust\t{%rax|rax}", (RMPADJUST)>, Requires<[In64BitMode]>;
H A DX86InstrSVM.td37 Requires<[In64BitMode]>;
45 Requires<[In64BitMode]>;
53 Requires<[In64BitMode]>;
61 "invlpga", []>, TB, Requires<[In64BitMode]>;
66 def : InstAlias<"vmrun\t{%rax|rax}", (VMRUN64), 0>, Requires<[In64BitMode]>;
68 def : InstAlias<"vmload\t{%rax|rax}", (VMLOAD64), 0>, Requires<[In64BitMode]>;
70 def : InstAlias<"vmsave\t{%rax|rax}", (VMSAVE64), 0>, Requires<[In64BitMode]>;
72 def : InstAlias<"invlpga\t{%rax, %ecx|rax, ecx}", (INVLPGA64), 0>, Requires<[In64BitMode]>;
H A DX86InstrVMX.td24 Requires<[In64BitMode]>;
32 Requires<[In64BitMode]>;
52 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
60 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
68 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
76 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
H A DX86InstrControl.td26 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
32 "ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
38 "{l}ret{|f}q", []>, Requires<[In64BitMode]>;
44 "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
54 def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>;
122 "jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>;
142 [(brind GR64:$dst)]>, Requires<[In64BitMode]>,
145 [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>,
179 [(X86NoTrackBrind GR64 : $dst)]>, Requires<[In64BitMode]>,
183 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>, NOTRACK;
[all …]
H A DX86InstrSystem.td64 Requires<[In64BitMode]>;
70 Requires<[In64BitMode]>;
131 Requires<[In64BitMode]>;
138 Requires<[In64BitMode]>;
150 Requires<[In64BitMode]>;
157 Requires<[In64BitMode]>;
180 Requires<[In64BitMode]>;
297 OpSize32, Requires<[In64BitMode]>;
299 OpSize32, Requires<[In64BitMode]>;
322 OpSize32, Requires<[In64BitMode]>;
[all …]
H A DX86InstrExtension.td22 "{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
34 "{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
158 Sched<[WriteALU]>, Requires<[In64BitMode]>;
162 Sched<[WriteLoad]>, Requires<[In64BitMode]>;
170 Sched<[WriteALU]>, OpSize16, Requires<[In64BitMode]>;
173 Sched<[WriteALU]>, OpSize32, Requires<[In64BitMode]>;
177 Sched<[WriteLoad]>, OpSize16, Requires<[In64BitMode]>;
180 Sched<[WriteLoad]>, OpSize32, Requires<[In64BitMode]>;
H A DX86InstrInfo.td1012 def In64BitMode : Predicate<"Subtarget->is64Bit()">,
1293 Requires<[In64BitMode]>;
1301 Requires<[In64BitMode]>;
1316 Requires<[In64BitMode]>;
1394 Requires<[In64BitMode]>;
1407 Requires<[In64BitMode]>;
1427 OpSize32, Requires<[In64BitMode]>;
1431 OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable;
1436 OpSize32, Requires<[In64BitMode]>;
1439 OpSize32, Requires<[In64BitMode]>;
[all …]
H A DX86InstrShiftRotate.td85 Requires<[In64BitMode]>;
103 Requires<[In64BitMode]>;
120 Requires<[In64BitMode]>;
187 Requires<[In64BitMode]>;
205 Requires<[In64BitMode]>;
222 Requires<[In64BitMode]>;
292 Requires<[In64BitMode]>;
310 Requires<[In64BitMode]>;
327 Requires<[In64BitMode]>;
414 "rcl{q}\t$dst", []>, Requires<[In64BitMode]>;
[all …]
H A DX86InstrAMX.td17 let Predicates = [HasAMXTILE, In64BitMode] in {
88 let Predicates = [HasAMXINT8, In64BitMode] in {
160 let Predicates = [HasAMXBF16, In64BitMode] in {
190 let Predicates = [HasAMXFP16, In64BitMode] in {
H A DX86InstrTDX.td18 let SchedRW = [WriteSystem], Predicates = [In64BitMode] in {
H A DX86InstrRAOINT.td35 let Predicates = [HasRAOINT, In64BitMode] in
H A DX86InstrCompiler.td91 (implicit EFLAGS)]>, Requires<[In64BitMode, IsLP64]>;
98 (implicit EFLAGS)]>, Requires<[In64BitMode, NotLP64]>;
118 Requires<[In64BitMode]>;
135 Requires<[In64BitMode]>;
161 Requires<[In64BitMode]>;
173 Requires<[In64BitMode]>, Sched<[WriteALU]>;
216 Requires<[In64BitMode]>;
225 Requires<[In64BitMode]>;
405 Requires<[NotLP64, In64BitMode]>;
448 Requires<[NotLP64, In64BitMode]>;
[all …]
H A DX86InstrArithmetic.td32 OpSize32, Requires<[In64BitMode]>;
105 Requires<[In64BitMode]>;
143 Requires<[In64BitMode]>;
311 Requires<[In64BitMode]>;
342 Requires<[In64BitMode]>;
388 Requires<[In64BitMode]>;
423 Requires<[In64BitMode]>;
480 let Predicates = [UseIncDec, In64BitMode] in {
528 let Predicates = [UseIncDec, In64BitMode] in {
998 let Predicates = [In64BitMode] in
[all …]
H A DX86InstrFPStack.td783 PS, Requires<[HasFXSR, In64BitMode]>;
792 PS, Requires<[HasFXSR, In64BitMode]>;
H A DX86InstrMMX.td558 let Uses = [RDI], Predicates = [HasMMX, HasSSE1,In64BitMode] in
H A DX86InstrFormats.td1014 : I<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX,In64BitMode]>;
1018 Requires<[HasMMX,In64BitMode]>;
H A DX86InstrSSE.td4086 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4097 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4984 TB, Requires<[HasSSE3, In64BitMode]>;
4992 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
4997 Requires<[In64BitMode]>;
H A DX86ISelLowering.cpp6389 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64); in getConstVector() local
6390 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) { in getConstVector()
6420 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64); in getConstVector() local
6421 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) { in getConstVector()
H A DX86InstrAVX512.td4075 Requires<[HasAVX512, In64BitMode]>;
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCInstr64Bit.td79 [(retflag)]>, Requires<[In64BitMode]>;
84 Requires<[In64BitMode]>;
88 Requires<[In64BitMode]>;
92 Requires<[In64BitMode]>;
95 Requires<[In64BitMode]>;
163 Requires<[In64BitMode]>;
169 Requires<[In64BitMode]>;
173 Requires<[In64BitMode]>;
176 Requires<[In64BitMode]>;
210 Requires<[In64BitMode]>;
[all …]
H A DPPCInstrVSX.td1298 Requires<[In64BitMode]>;
1304 Requires<[In64BitMode]>;
1316 Requires<[In64BitMode]>;
1322 Requires<[In64BitMode]>;
1349 []>, Requires<[In64BitMode]>;
1353 []>, Requires<[In64BitMode]>;
H A DPPCInstrInfo.td701 def In64BitMode : Predicate<"Subtarget->isPPC64()">;
5029 let Predicates = [In64BitMode] in
/openbsd-src/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsInstrFPU.td105 // S64 - single precision in 32 64bit fp registers (In64BitMode)
107 // D64 - double precision in 32 64bit fp registers (In64BitMode)
/openbsd-src/gnu/llvm/llvm/include/llvm/Target/
H A DTarget.td1592 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1597 /// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
/openbsd-src/gnu/llvm/llvm/docs/
H A DCodeGenerator.rst1762 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;