Searched refs:FinalReg (Results 1 – 3 of 3) sorted by relevance
1682 unsigned FinalReg = FinalOp.Mem.BaseReg; in VerifyAndAdjustOperands() local1703 bool IsSI = IsSIReg(FinalReg); in VerifyAndAdjustOperands()1704 FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI); in VerifyAndAdjustOperands()1706 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()1716 FinalOp.Mem.BaseReg = FinalReg; in VerifyAndAdjustOperands()
943 FinalReg = InProlog ? X86::RDX in emitStackProbeInlineWindowsCoreCLR64() local1004 BuildMI(&MBB, DL, TII.get(X86::CMOV64rr), FinalReg) in emitStackProbeInlineWindowsCoreCLR64()1022 BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg); in emitStackProbeInlineWindowsCoreCLR64()1027 RoundMBB->addLiveIn(FinalReg); in emitStackProbeInlineWindowsCoreCLR64()1029 .addReg(FinalReg) in emitStackProbeInlineWindowsCoreCLR64()
1588 unsigned FinalReg = SubReg; in buildSpillLoadStore() local1656 FinalReg) in buildSpillLoadStore()