| /openbsd-src/gnu/llvm/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 211 FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures); in InitMCProcessorInfo()
222 FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures); in setDefaultFeatures()
242 FeatureBits.flip(FB); in ToggleFeature()
243 return FeatureBits; in ToggleFeature()
247 FeatureBits ^= FB; in ToggleFeature()
248 return FeatureBits; in ToggleFeature()
253 SetImpliedBits(FeatureBits, FB, ProcFeatures); in SetFeatureBitsTransitively()
254 return FeatureBits; in SetFeatureBitsTransitively()
261 FeatureBits.reset(I); in ClearFeatureBitsTransitively()
262 ClearImpliedBits(FeatureBits, I, ProcFeatures); in ClearFeatureBitsTransitively()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVBaseInfo.cpp | 39 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, in computeTargetABI() argument
43 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; in computeTargetABI()
68 auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits); in computeTargetABI()
99 void validate(const Triple &TT, const FeatureBitset &FeatureBits) { in validate() argument
100 if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) in validate()
102 if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit]) in validate()
104 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) in validate()
106 if (FeatureBits[RISCV::Feature32Bit] && in validate()
107 FeatureBits[RISCV::Feature64Bit]) in validate()
112 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) { in parseFeatureBits() argument
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| H A D | RISCVBaseInfo.h | 393 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
410 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
413 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits);
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| /openbsd-src/gnu/llvm/llvm/include/llvm/MC/ |
| H A D | MCSubtargetInfo.h | 92 FeatureBitset FeatureBits; // Feature bits for current CPU + FS variable
112 const FeatureBitset& getFeatureBits() const { return FeatureBits; } in getFeatureBits()
114 FeatureBits = FeatureBits_; in setFeatureBits()
120 return FeatureBits[Feature]; in hasFeature()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 168 FeatureBitset FeatureBits = getFeatureBits(); in initializeSubtargetDependencies() local
170 setFeatureBits(FeatureBits.reset(Hexagon::FeatureDuplex)); in initializeSubtargetDependencies()
171 setFeatureBits(Hexagon_MC::completeHVXFeatures(FeatureBits)); in initializeSubtargetDependencies()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/Disassembler/ |
| H A D | RISCVDisassembler.cpp | 64 const FeatureBitset &FeatureBits = in DecodeGPRRegisterClass() local
66 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; in DecodeGPRRegisterClass()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/Disassembler/ |
| H A D | CSKYDisassembler.cpp | 215 const FeatureBitset &FeatureBits = in DecodeGPRPairRegisterClass() local
217 bool hasHighReg = FeatureBits[CSKY::FeatureHighreg]; in DecodeGPRPairRegisterClass()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 919 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); in AddThumbPredicate() local
946 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) in AddThumbPredicate()
2547 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); in DecodeHINTInstruction() local
2558 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) in DecodeHINTInstruction()
2792 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); in DecodeSETPANInstruction() local
2794 if (!FeatureBits[ARM::HasV8_1aOps] || in DecodeSETPANInstruction()
2795 !FeatureBits[ARM::HasV8Ops]) in DecodeSETPANInstruction()
4831 const FeatureBitset &FeatureBits = in DecodeThumbTableBranch() local
4838 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; in DecodeThumbTableBranch()
4976 const FeatureBitset &FeatureBits = in DecodeMSRMask() local
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMInstPrinter.cpp | 866 const FeatureBitset &FeatureBits = STI.getFeatureBits(); in printMSRMaskOperand() local
867 if (FeatureBits[ARM::FeatureMClass]) { in printMSRMaskOperand()
873 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) { in printMSRMaskOperand()
883 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { in printMSRMaskOperand()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 215 FeatureBitset FeatureBits = FeatureBitStack.pop_back_val(); in popFeatureBits() local
216 copySTI().setFeatureBits(FeatureBits); in popFeatureBits()
217 setAvailableFeatures(ComputeAvailableFeatures(FeatureBits)); in popFeatureBits()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 480 FeatureBitset FeatureBits = STI.getFeatureBits(); in selectArch() local
481 FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask; in selectArch()
482 STI.setFeatureBits(FeatureBits); in selectArch()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 5430 const FeatureBitset &FeatureBits = Subtarget->getFeatureBits(); in getMClassRegisterMask() local
5431 if (!TheReg || !TheReg->hasRequiredFeatures(FeatureBits)) in getMClassRegisterMask()
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