| /openbsd-src/usr.bin/awk/ |
| H A D | awk.h | 153 #define FSIN 9 macro
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| H A D | lex.c | 87 { "sin", FSIN, BLTIN },
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| H A D | run.c | 2092 case FSIN: in bltin()
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| /openbsd-src/gnu/llvm/llvm/include/llvm/IR/ |
| H A D | ConstrainedOps.def | 95 DAG_FUNCTION(sin, 1, 1, experimental_constrained_sin, FSIN)
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| /openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 914 FSIN, enumerator
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| H A D | BasicTTIImpl.h | 1771 ISD = ISD::FSIN; in getTypeBasedIntrinsicInstrCost()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 95 setOperationAction({ISD::FCOS, ISD::FSIN}, MVT::f32, Custom); in R600TargetLowering()
409 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
703 case ISD::FSIN: in LowerTrig()
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| H A D | AMDGPUISelLowering.cpp | 452 ISD::FSQRT, ISD::FSIN, ISD::FSUB, ISD::FNEG, in AMDGPUTargetLowering()
570 case ISD::FSIN: in fnegFoldsIntoOp()
3979 case ISD::FSIN: in performFNegCombine()
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| H A D | SIISelLowering.cpp | 474 setOperationAction({ISD::FSIN, ISD::FCOS, ISD::FDIV}, MVT::f32, Custom); in SITargetLowering()
518 {ISD::FP_ROUND, ISD::FCOS, ISD::FSIN, ISD::FROUND, ISD::FPTRUNC_ROUND}, in SITargetLowering()
4700 case ISD::FSIN: in LowerOperation()
9363 case ISD::FSIN: in LowerTrig()
10140 case ISD::FSIN: in isCanonicalized()
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| H A D | AMDGPUISelDAGToDAG.cpp | 153 case ISD::FSIN: in fp16SrcZerosHighBits()
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| /openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 202 case ISD::FSIN: return "fsin"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 123 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
1264 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
2272 case ISD::FSIN: in PromoteFloatResult()
2638 case ISD::FSIN: in SoftPromoteHalfResult()
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| H A D | LegalizeDAG.cpp | 2233 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2234 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3228 case ISD::FSIN: in ExpandNode()
4049 case ISD::FSIN: in ConvertNodeToLibcall()
4879 case ISD::FSIN: in PromoteNode()
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| H A D | LegalizeVectorOps.cpp | 369 case ISD::FSIN: in LegalizeOp()
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| H A D | LegalizeVectorTypes.cpp | 105 case ISD::FSIN: in ScalarizeVectorResult()
1059 case ISD::FSIN: in SplitVectorResult()
4089 case ISD::FSIN: in WidenVectorResult()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86ScheduleAtom.td | 928 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
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| H A D | X86InstrFPStack.td | 768 def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>;
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1764 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1769 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1774 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 119 ISD::NodeType FPOpToExpand[] = {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in CSKYTargetLowering()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 145 setOperationAction(ISD::FSIN, MVT::f32, Expand); in LoongArchTargetLowering()
161 setOperationAction(ISD::FSIN, MVT::f64, Expand); in LoongArchTargetLowering()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1589 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1634 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 383 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
388 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
397 setOperationAction(ISD::FSIN , MVT::f64, Custom); in PPCTargetLowering()
403 setOperationAction(ISD::FSIN , MVT::f32, Custom); in PPCTargetLowering()
845 setOperationAction(ISD::FSIN, VT, Expand); in PPCTargetLowering()
1172 setOperationAction(ISD::FSIN, MVT::f128, Expand); in PPCTargetLowering()
11301 case ISD::FSIN: return lowerSin(Op, DAG); in LowerOperation()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 419 setOperationAction(ISD::FSIN, MVT::f32, Expand); in MipsTargetLowering()
420 setOperationAction(ISD::FSIN, MVT::f64, Expand); in MipsTargetLowering()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 124 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
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| /openbsd-src/gnu/llvm/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 366 setOperationAction(ISD::FSIN, VT, Expand); in addMVEVectorTypes()
875 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); in ARMTargetLowering()
896 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); in ARMTargetLowering()
912 setOperationAction(ISD::FSIN, MVT::v2f32, Expand); in ARMTargetLowering()
1045 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1438 setOperationAction(ISD::FSIN, MVT::f64, Expand); in ARMTargetLowering()
1439 setOperationAction(ISD::FSIN, MVT::f32, Expand); in ARMTargetLowering()
1522 setOperationAction(ISD::FSIN, MVT::f16, Promote); in ARMTargetLowering()
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