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Searched refs:FP16 (Results 1 – 20 of 20) sorted by relevance

/openbsd-src/gnu/llvm/clang/include/clang/Basic/
H A Darm_fp16.td1 //===--- arm_fp16.td - ARM FP16 compiler interface ------------------------===//
9 // This file defines the TableGen definitions from which the ARM FP16 header
16 // ARMv8.2-A FP16 intrinsics.
H A DBuiltinsX86_64.def141 // AMX_FP16 FP16
H A Darm_neon.td1651 // ARMv8.2-A FP16 vector intrinsics for A32/A64.
1654 // ARMv8.2-A FP16 one-operand vector intrinsics.
1692 // ARMv8.2-A FP16 two-operands vector intrinsics.
1745 // ARMv8.2-A FP16 three-operands vector intrinsics.
1751 // ARMv8.2-A FP16 lane vector intrinsics.
1775 // ARMv8.2-A FP16 vector intrinsics for A64 only.
1799 // ARMv8.2-A FP16 lane vector intrinsics.
1850 // ARMv8.2-A FP16 reduction vector intrinsics.
1882 // v8.2-A FP16 fused multiply-add long instructions.
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86InstrAMX.td189 //AMX-FP16
H A DX86.td182 // FIXME: FP16 scalar intrinsics use the type v8f16, which is supposed to be
184 // FIXME: FP16 conversion between f16 and i64 customize type v8i64, which is
H A DX86InstrSSE.td4031 // Always select FP16 instructions if available.
H A DX86InstrAVX512.td11751 // Always select FP16 instructions if available.
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMInstrFormats.td1675 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
2024 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
2054 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
2082 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
2113 let isUnpredicable = 1; // FP16 instructions cannot in general be conditional
H A DARMISelDAGToDAG.cpp136 bool IsAddressingMode5(SDValue N, SDValue &Base, SDValue &Offset, bool FP16);
987 bool FP16) { in IsAddressingMode5() argument
1007 const int Scale = FP16 ? 2 : 4; in IsAddressingMode5()
1023 if (FP16) in IsAddressingMode5()
1035 if (FP16) in IsAddressingMode5()
H A DARM.td43 // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64.td107 "Full FP16 (FEAT_FP16)", [FeatureFPARMv8]>;
110 "Enable FP16 FML instructions (FEAT_FHM)", [FeatureFullFP16]>;
H A DAArch64InstrInfo.td1135 // ARMv8.2-A FP16 Fused Multiply-Add Long
1263 // inside the multiclass as the FP16 versions need different predicates.
4222 // Pattern for FP16 immediates
6760 // Patterns for FP16 Intrinsics - requires reg copy to/from as i16s not supported.
/openbsd-src/gnu/llvm/llvm/docs/
H A DReleaseNotes.rst310 * Support ISA of ``AMX-FP16`` which contains ``tdpfp16ps`` instruction.
/openbsd-src/gnu/llvm/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td532 // v8.2-A FP16 Fused Multiply-Add Long
H A DIntrinsicsX86.td5350 // AMX-FP16 - Intel FP16 AMX extensions
H A DIntrinsicsNVVM.td224 // FP16 ops are identified by accumulator & result type.
/openbsd-src/gnu/llvm/clang/docs/
H A DReleaseNotes.rst967 - Add ISA of ``AMX-FP16`` which support ``_tile_dpfp16ps``.
H A DLanguageExtensions.rst786 AVX512-FP16, ``_Float16`` arithmetic is performed using that native support.
H A DUsersManual.rst1777 * ``_Float16`` on X86 targets without ``AVX512-FP16``.
/openbsd-src/gnu/llvm/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td1018 // Loads FP16 constant into a register.