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Searched refs:ExtOpc (Results 1 – 16 of 16) sorted by relevance

/openbsd-src/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp391 bool isRegOffOpcode(unsigned ExtOpc) const ;
392 unsigned getRegOffOpcode(unsigned ExtOpc) const;
393 unsigned getDirectRegReplacement(unsigned ExtOpc) const;
866 unsigned HCE::getRegOffOpcode(unsigned ExtOpc) const { in getRegOffOpcode()
870 switch (ExtOpc) { in getRegOffOpcode()
875 const MCInstrDesc &D = HII->get(ExtOpc); in getRegOffOpcode()
883 switch (ExtOpc) { in getRegOffOpcode()
956 if (!isStoreImmediate(ExtOpc)) in getRegOffOpcode()
957 return ExtOpc; in getRegOffOpcode()
966 unsigned HCE::getDirectRegReplacement(unsigned ExtOpc) const { in getDirectRegReplacement()
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H A DHexagonBitSimplify.cpp2542 unsigned ExtOpc = 0; in simplifyExtractLow() local
2545 ExtOpc = Signed ? Hexagon::A2_sxtb : Hexagon::A2_zxtb; in simplifyExtractLow()
2547 ExtOpc = Signed ? Hexagon::A2_sxth : Hexagon::A2_zxth; in simplifyExtractLow()
2549 ExtOpc = Hexagon::A2_andir; in simplifyExtractLow()
2551 if (ExtOpc == 0) { in simplifyExtractLow()
2552 ExtOpc = in simplifyExtractLow()
2564 if (!validateReg({R,SR}, ExtOpc, 1)) in simplifyExtractLow()
2568 if (MI->getOpcode() == ExtOpc) { in simplifyExtractLow()
2580 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR) in simplifyExtractLow()
2582 switch (ExtOpc) { in simplifyExtractLow()
H A DHexagonISelLoweringHVX.cpp1585 unsigned ExtOpc = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in resizeToWidth() local
1586 return DAG.getNode(ExtOpc, dl, ResTy, VecV); in resizeToWidth()
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp503 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, in buildExtOrTrunc() argument
506 assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || in buildExtOrTrunc()
507 TargetOpcode::G_SEXT == ExtOpc) && in buildExtOrTrunc()
517 Opcode = ExtOpc; in buildExtOrTrunc()
H A DLegalizerHelper.cpp2116 unsigned ExtOpc = MI.getOpcode() == TargetOpcode::G_CTTZ || in widenScalar() local
2120 auto MIBSrc = MIRBuilder.buildInstr(ExtOpc, {WideTy}, {SrcReg}); in widenScalar()
2386 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( in widenScalar() local
2388 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || in widenScalar()
2389 ExtOpc == TargetOpcode::G_ANYEXT) && in widenScalar()
2392 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) in widenScalar()
H A DCombinerHelper.cpp492 static unsigned getExtLoadOpcForExtend(unsigned ExtOpc) { in getExtLoadOpcForExtend() argument
494 switch (ExtOpc) { in getExtLoadOpcForExtend()
/openbsd-src/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp998 unsigned ExtOpc = ISD::ANY_EXTEND) { in customLegalizeToWOp() argument
1007 NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOp()
1012 NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOp()
1013 SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1)); in customLegalizeToWOp()
/openbsd-src/gnu/llvm/llvm/lib/Transforms/InstCombine/
H A DInstCombineCalls.cpp2807 Instruction::CastOps ExtOpc = Instruction::CastOps::CastOpsEnd; in visitCallInst() local
2809 ExtOpc = cast<CastInst>(Arg)->getOpcode(); in visitCallInst()
2811 (ExtOpc == Instruction::CastOps::ZExt)) in visitCallInst()
2815 Res = Builder.CreateCast(ExtOpc, Res, II->getType()); in visitCallInst()
/openbsd-src/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2785 unsigned ExtOpc = in lowerScalarSplat() local
2787 Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar); in lowerScalarSplat()
2852 unsigned ExtOpc = in lowerScalarInsert() local
2854 Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar); in lowerScalarInsert()
5455 unsigned ExtOpc = in lowerVectorIntrinsicScalars() local
5457 ScalarOp = DAG.getNode(ExtOpc, DL, XLenVT, ScalarOp); in lowerVectorIntrinsicScalars()
7637 unsigned ExtOpc = ISD::ANY_EXTEND) { in customLegalizeToWOp() argument
7640 SDValue NewOp0 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOp()
7641 SDValue NewOp1 = DAG.getNode(ExtOpc, DL, MVT::i64, N->getOperand(1)); in customLegalizeToWOp()
7873 unsigned ExtOpc = ISD::ANY_EXTEND; in ReplaceNodeResults() local
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/openbsd-src/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp1907 unsigned ExtOpc, in extendLow32IntoHigh32() argument
1910 if (ExtOpc == AMDGPU::G_ZEXT) { in extendLow32IntoHigh32()
1912 } else if (ExtOpc == AMDGPU::G_SEXT) { in extendLow32IntoHigh32()
1924 assert(ExtOpc == AMDGPU::G_ANYEXT && "not an integer extension"); in extendLow32IntoHigh32()
/openbsd-src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h757 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
/openbsd-src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1312 unsigned ExtOpc = in PromoteOperand() local
1314 return DAG.getNode(ExtOpc, DL, PVT, Op); in PromoteOperand()
6359 unsigned ExtOpc = N0.getOpcode(); in visitAND() local
6362 (ExtOpc != ISD::ZERO_EXTEND || !TLI.isZExtFree(N0Op0, VT)) && in visitAND()
6369 DAG.getNode(ExtOpc, DL, VT, N0Op0.getOperand(1))); in visitAND()
6371 DAG.getNode(ExtOpc, DL, VT, N0Op0.getOperand(0)), in visitAND()
11867 unsigned ExtOpc, in ExtendUsesToFormExtLoad() argument
11880 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { in ExtendUsesToFormExtLoad()
11882 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) in ExtendUsesToFormExtLoad()
12204 ISD::NodeType ExtOpc) { in tryToFoldExtOfLoad() argument
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H A DLegalizeIntegerTypes.cpp5444 unsigned ExtOpc = ISD::ANY_EXTEND; in PromoteIntRes_BUILD_VECTOR() local
5449 ExtOpc = NOutExtOpc; in PromoteIntRes_BUILD_VECTOR()
5450 Op = DAG.getNode(ExtOpc, dl, NOutVTElem, Op); in PromoteIntRes_BUILD_VECTOR()
H A DTargetLowering.cpp5262 ISD::NodeType ExtOpc = in LowerAsmOperandForConstraint() local
5265 ExtOpc == ISD::ZERO_EXTEND ? C->getZExtValue() : C->getSExtValue(); in LowerAsmOperandForConstraint()
/openbsd-src/gnu/llvm/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp22237 static SDValue SplitAndExtendv16i1(unsigned ExtOpc, MVT VT, SDValue In, in SplitAndExtendv16i1() argument
22244 Lo = DAG.getNode(ExtOpc, dl, MVT::v8i16, Lo); in SplitAndExtendv16i1()
22245 Hi = DAG.getNode(ExtOpc, dl, MVT::v8i16, Hi); in SplitAndExtendv16i1()
25916 unsigned ExtOpc = in LowerEXTEND_VECTOR_INREG() local
25919 return DAG.getNode(ExtOpc, dl, VT, In); in LowerEXTEND_VECTOR_INREG()
30727 unsigned ExtOpc = Opc == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerShift() local
30728 R = DAG.getNode(ExtOpc, dl, ExtVT, R); in LowerShift()
33404 unsigned ExtOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in ReplaceNodeResults() local
33405 SDValue Op0 = DAG.getNode(ExtOpc, dl, MVT::v2i64, N->getOperand(0)); in ReplaceNodeResults()
33406 SDValue Op1 = DAG.getNode(ExtOpc, dl, MVT::v2i64, N->getOperand(1)); in ReplaceNodeResults()
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H A DX86TargetTransformInfo.cpp3002 unsigned ExtOpc = in getCastInstrCost() local
3008 ExtCost = getCastInstrCost(ExtOpc, ExtSrc, Src, CCH, CostKind); in getCastInstrCost()