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Searched refs:DUP (Results 1 – 25 of 33) sorted by relevance

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/openbsd-src/gnu/usr.bin/binutils-2.17/opcodes/
H A Dmt-opc.c574 …,', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTX…
580 …,', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTX…
586 …, '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTX…
592 …, '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTX…
598 …, '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTX…
604 …, '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTX…
610 …',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTX…
616 …',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTX…
622 …',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTX…
628 …',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTX…
[all …]
/openbsd-src/sys/dev/pci/drm/i915/
H A Di915_params.c300 #define DUP(T, x, ...) _param_dup(&dest->x); in i915_params_copy() macro
301 I915_PARAMS_FOR_EACH(DUP); in i915_params_copy()
302 #undef DUP in i915_params_copy()
/openbsd-src/usr.bin/hexdump/
H A Ddisplay.c252 if (vflag != DUP) in get()
274 if (vflag == DUP || vflag == FIRST) in get()
280 vflag = DUP; in get()
H A Dhexdump.h72 enum _vflag { ALL, DUP, FIRST, WAIT }; /* -v values */ enumerator
/openbsd-src/gnu/llvm/llvm/lib/Target/ARM/
H A DARMScheduleSwift.td933 (instregex "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
935 (instregex "VLD1(LN|DUP)(d|q)(8|16|32)(wb|_UPD)",
939 (instregex "VLD2(DUP|LN)(d|q)(8|16|32|8x2|16x2|32x2)$",
953 (instregex "VLD3(DUP|LN)(d|q)(8|16|32)$",
954 "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
957 (instregex "VLD3(LN|DUP)(d|q)(8|16|32)_UPD")>;
960 (instregex "VLD3(LN|DUP)(d|q)(8|16|32)Pseudo_UPD")>;
964 (instregex "VLD4(LN|DUP)(d|q)(8|16|32)$",
965 "VLD4(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
969 (instregex "VLD4(DUP|LN)(d|q)(8|16|32)_UPD")>;
[all …]
H A DARMScheduleA57.td145 "VLD(3|4)(DUP|LN)?(d|q)(WB_fixed_|WB_register_)?Asm",
147 "VST(3|4)(DUP|LN)?(d|q)(WB_fixed_|WB_register_)?Asm",
1276 "VLD1(LN|DUP)(d|q)(8|16|32)$", "VLD1(LN|DUP)(d|q)(8|16|32)Pseudo$")>;
1278 "VLD1(LN|DUP)(d|q)(8|16|32)(wb|_UPD)", "VLD1LNq(8|16|32)Pseudo_UPD")>;
1293 (instregex "VLD2(DUP|LN)(d|q)(8|16|32|8x2|16x2|32x2)$",
H A DARMScheduleM55.td350 def : InstRW<[M55Write2IntE2], (instregex "MVE_V(D|I)?W?DUP")>;
/openbsd-src/gnu/usr.bin/gcc/gcc/java/
H A Djavaop.def199 JAVAOP (dup, 89, STACK, DUP, 1)
202 JAVAOP (dup2, 92, STACK, DUP, 2)
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td909 def : InstRW<[FalkorWr_1GTOV_1cyc], (instregex "^DUP(v8i8|v4i16|v2i32)(gpr|lane)$")>;
910 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^DUP(v16i8|v8i16)(gpr|lane)$")>;
911 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^DUP(i8|i16|i32|i64)$")>;
937 def : InstRW<[FalkorWr_2GTOV_1cyc], (instregex "^DUP(v4i32|v2i64)(gpr|lane)$")>;
H A DAArch64SchedCyclone.td367 // DUP V,R
370 // DUP V,V[x] is a WriteV.
H A DAArch64SchedTSV110.td673 def : InstRW<[TSV110Wr_2cyc_1FSU1_1FSU2], (instregex "^(DUP|INS)v.+lane")>;
681 def : InstRW<[TSV110Wr_4cyc_1F], (instregex "^(INS|DUP)v.+gpr")>;
H A DAArch64ISelLowering.h172 DUP, enumerator
H A DAArch64InstrInfo.td636 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
5638 // AdvSIMD scalar DUP instruction
5641 defm DUP : SIMDScalarDUP<"mov">;
5704 // AdvSIMD INS/DUP instructions
5723 // DUP from a 64-bit register to a 64-bit register is just a copy
5790 Instruction DUP, SDNodeXForm IdxXFORM> {
5793 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
5797 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
5808 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
5812 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
[all …]
H A DAArch64SchedA55.td366 def : InstRW<[CortexA55WriteFPALU_F2], (instregex "^DUP(v2i64|v4i32|v8i16|v16i8)")>;
H A DAArch64ISelLowering.cpp2119 case AArch64ISD::DUP: { in computeKnownBitsForTargetNode()
2362 MAKE_CASE(AArch64ISD::DUP) in getTargetNodeName()
2841 if (N->getOpcode() != AArch64ISD::DUP) in isZerosVector()
4924 return DAG.getNode(AArch64ISD::DUP, dl, MVT::v1i64, N); in LowerINTRINSIC_WO_CHAIN()
11495 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(), in LowerVECTOR_SHUFFLE()
11501 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane)); in LowerVECTOR_SHUFFLE()
12347 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value); in LowerBUILD_VECTOR()
12405 Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue); in LowerBUILD_VECTOR()
12787 if (Op.getOpcode() != AArch64ISD::DUP && in isPow2Splat()
16230 if (N->getOpcode() == AArch64ISD::DUP || N->getOpcode() == ISD::SPLAT_VECTOR) in isConstantSplatVectorMaskForType()
[all …]
H A DAArch64SchedExynosM3.td673 def : InstRW<[M3WriteNSHF1], (instregex "^DUP(i8|i16|i32|i64)$")>;
H A DAArch64SchedKryoDetails.td573 (instregex "DUP(v8i8|v4i16|v2i32)(gpr|lane)")>;
579 (instregex "DUP(v16i8|v8i16|v4i32|v2i64)(gpr|lane)")>;
H A DAArch64SchedA57.td530 def : InstRW<[A57Write_8cyc_1L_1V], (instregex "^DUP(i8|i16|i32|i64)$")>;
H A DAArch64SchedExynosM4.td814 def : InstRW<[M4WriteNSHF1], (instregex "^DUP(i8|i16|i32|i64)$")>;
H A DAArch64SchedExynosM5.td852 def : InstRW<[M5WriteNSHF2], (instregex "^DUP(i8|i16|i32|i64)$")>;
H A DAArch64ISelDAGToDAG.cpp195 else if (Op.getOperand(1).getOpcode() == AArch64ISD::DUP && in SelectRoundingVLShr()
214 case AArch64ISD::DUP: in SelectDupZeroOrUndef()
232 case AArch64ISD::DUP: in SelectDupZero()
H A DAArch64InstrFormats.td7479 // AdvSIMD INS/DUP instructions
7931 // AdvSIMD scalar DUP
7981 // 'DUP' mnemonic aliases.
8533 // Patterns for f16: DUPLANE, DUP scalar and vector_extract.
8560 // 2 variants for the .2s version: DUPLANE from 128-bit and DUP scalar.
8572 // 2 variants for the .4s version: DUPLANE from 128-bit and DUP scalar.
8583 // 2 variants for the .2d version: DUPLANE from 128-bit and DUP scalar.
H A DAArch64SchedThunderX3T110.td1613 def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^DUP(i8|i16|i32|i64)$")>;
/openbsd-src/gnu/usr.bin/binutils-2.17/cpu/
H A Dmt.opc259 if (strncmp (*strp, "dup", 3) == 0 || strncmp (*strp, "DUP", 3) == 0)
H A Dmt.cpu403 (values (DUP 1) (XX 0))

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