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Searched refs:DP (Results 1 – 25 of 142) sorted by relevance

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/openbsd-src/sys/dev/pci/drm/amd/display/dc/dce/
H A Ddce_link_encoder.h54 SRI(DP_CONFIG, DP, id), \
55 SRI(DP_DPHY_CNTL, DP, id), \
56 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
57 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
58 SRI(DP_DPHY_SYM0, DP, id), \
59 SRI(DP_DPHY_SYM1, DP, id), \
60 SRI(DP_DPHY_SYM2, DP, id), \
61 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
62 SRI(DP_LINK_CNTL, DP, id), \
63 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
[all …]
H A Ddce_stream_encoder.h84 SRI(DP_MSE_RATE_CNTL, DP, id), \
85 SRI(DP_MSE_RATE_UPDATE, DP, id), \
86 SRI(DP_PIXEL_FORMAT, DP, id), \
87 SRI(DP_SEC_CNTL, DP, id), \
88 SRI(DP_STEER_FIFO, DP, id), \
89 SRI(DP_VID_M, DP, id), \
90 SRI(DP_VID_N, DP, id), \
91 SRI(DP_VID_STREAM_CNTL, DP, id), \
92 SRI(DP_VID_TIMING, DP, id), \
93 SRI(DP_SEC_AUD_N, DP, id), \
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_dio_link_encoder.h36 SRI(DP_CONFIG, DP, id), \
37 SRI(DP_DPHY_CNTL, DP, id), \
38 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
39 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
40 SRI(DP_DPHY_SYM0, DP, id), \
41 SRI(DP_DPHY_SYM1, DP, id), \
42 SRI(DP_DPHY_SYM2, DP, id), \
43 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
44 SRI(DP_LINK_CNTL, DP, id), \
45 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
[all …]
H A Ddcn30_dio_stream_encoder.h76 SRI(DP_DB_CNTL, DP, id), \
77 SRI(DP_MSA_MISC, DP, id), \
78 SRI(DP_MSA_VBID_MISC, DP, id), \
79 SRI(DP_MSA_COLORIMETRY, DP, id), \
80 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
81 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
82 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
83 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
84 SRI(DP_MSE_RATE_CNTL, DP, id), \
85 SRI(DP_MSE_RATE_UPDATE, DP, id), \
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn301/
H A Ddcn301_dio_link_encoder.h37 SRI(DP_CONFIG, DP, id), \
38 SRI(DP_DPHY_CNTL, DP, id), \
39 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
40 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
41 SRI(DP_DPHY_SYM0, DP, id), \
42 SRI(DP_DPHY_SYM1, DP, id), \
43 SRI(DP_DPHY_SYM2, DP, id), \
44 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
45 SRI(DP_LINK_CNTL, DP, id), \
46 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
[all …]
/openbsd-src/gnu/llvm/llvm/lib/IR/
H A DDiagnosticInfo.cpp62 void DiagnosticInfoInlineAsm::print(DiagnosticPrinter &DP) const { in print()
63 DP << getMsgStr(); in print()
65 DP << " at line " << getLocCookie(); in print()
75 void DiagnosticInfoResourceLimit::print(DiagnosticPrinter &DP) const { in print()
76 DP << getLocationStr() << ": " << getResourceName() << " (" in print()
81 void DiagnosticInfoDebugMetadataVersion::print(DiagnosticPrinter &DP) const { in print()
82 DP << "ignoring debug info with an invalid version (" << getMetadataVersion() in print()
87 DiagnosticPrinter &DP) const { in print()
88 DP << "ignoring invalid debug info in " << getModule().getModuleIdentifier(); in print()
91 void DiagnosticInfoSampleProfile::print(DiagnosticPrinter &DP) const { in print()
[all …]
/openbsd-src/sys/dev/pci/drm/i915/display/
H A Dg4x_dp.c120 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; in intel_dp_prepare()
123 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; in intel_dp_prepare()
124 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); in intel_dp_prepare()
130 intel_dp->DP |= DP_SYNC_HS_HIGH; in intel_dp_prepare()
132 intel_dp->DP |= DP_SYNC_VS_HIGH; in intel_dp_prepare()
133 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; in intel_dp_prepare()
136 intel_dp->DP |= DP_ENHANCED_FRAMING; in intel_dp_prepare()
138 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); in intel_dp_prepare()
140 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; in intel_dp_prepare()
148 intel_dp->DP |= DP_COLOR_RANGE_16_235; in intel_dp_prepare()
[all …]
H A Dintel_pps.c95 u32 DP; in vlv_power_sequencer_kick() local
112 DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
113 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; in vlv_power_sequencer_kick()
114 DP |= DP_PORT_WIDTH(1); in vlv_power_sequencer_kick()
115 DP |= DP_LINK_TRAIN_PAT_1; in vlv_power_sequencer_kick()
118 DP |= DP_PIPE_SEL_CHV(pipe); in vlv_power_sequencer_kick()
120 DP |= DP_PIPE_SEL(pipe); in vlv_power_sequencer_kick()
146 intel_de_write(dev_priv, intel_dp->output_reg, DP); in vlv_power_sequencer_kick()
149 intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN); in vlv_power_sequencer_kick()
152 intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN); in vlv_power_sequencer_kick()
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn314/
H A Ddcn314_dio_stream_encoder.h77 SRI(DP_DB_CNTL, DP, id), \
78 SRI(DP_MSA_MISC, DP, id), \
79 SRI(DP_MSA_VBID_MISC, DP, id), \
80 SRI(DP_MSA_COLORIMETRY, DP, id), \
81 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
82 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
83 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
84 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
85 SRI(DP_MSE_RATE_CNTL, DP, id), \
86 SRI(DP_MSE_RATE_UPDATE, DP, id), \
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_link_encoder.h47 SRI(DP_CONFIG, DP, id), \
48 SRI(DP_DPHY_CNTL, DP, id), \
49 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
50 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
51 SRI(DP_DPHY_SYM0, DP, id), \
52 SRI(DP_DPHY_SYM1, DP, id), \
53 SRI(DP_DPHY_SYM2, DP, id), \
54 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
55 SRI(DP_LINK_CNTL, DP, id), \
56 SRI(DP_LINK_FRAMING_CNTL, DP, id), \
[all …]
H A Ddcn10_stream_encoder.h74 SRI(DP_DB_CNTL, DP, id), \
75 SRI(DP_MSA_MISC, DP, id), \
76 SRI(DP_MSA_VBID_MISC, DP, id), \
77 SRI(DP_MSA_COLORIMETRY, DP, id), \
78 SRI(DP_MSA_TIMING_PARAM1, DP, id), \
79 SRI(DP_MSA_TIMING_PARAM2, DP, id), \
80 SRI(DP_MSA_TIMING_PARAM3, DP, id), \
81 SRI(DP_MSA_TIMING_PARAM4, DP, id), \
82 SRI(DP_MSE_RATE_CNTL, DP, id), \
83 SRI(DP_MSE_RATE_UPDATE, DP, id), \
[all …]
/openbsd-src/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCScheduleP9.td102 // Four DP (Floating Point) units in total. Two even, two Odd.
103 def DP : ProcResource<4>;
105 //Even DP pipelines
106 let Super = DP;
109 //Odd DP pipelines
110 let Super = DP;
244 // DP Unit
245 // A DP unit may take from 2 to 36 cycles to complete.
246 // Some DP operations keep the unit busy for up to 10 cycles.
247 def P9_DP_5C : SchedWriteRes<[DP]> {
[all …]
H A DP9InstrResources.td26 // - Four DP (Floating Point) units. One on each slice. P9_DP_*
107 (instregex "XSMAX(C|J)?DP$"),
108 (instregex "XSMIN(C|J)?DP$"),
109 (instregex "XSCMP(EQ|EXP|GE|GT|O|U)DP$"),
290 // 7 cycle DP vector operation that uses an entire superslice.
291 // Uses both DP units (the even DPE and odd DPO units), two pipelines (EXECE,
401 // 5 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three
409 // 7 cycle Restricted DP operation. One DP unit, one EXEC pipeline and all three
452 // 7 cycle Restricted DP operation and one 3 cycle ALU operation.
453 // These operations can be done in parallel. The DP is restricted so we need a
[all …]
H A DREADME_P9.txt306 - DP/QP Compare Exponents: xscmpexpdp xscmpexpqp
309 - DP Compare ==, >=, >, !=: xscmpeqdp xscmpgedp xscmpgtdp xscmpnedp
327 - Convert DP -> QP: xscvdpqp
334 - Round & Convert QP -> DP (dword[1] is set to zero): xscvqpdp xscvqpdpo
354 - (Round &) Convert DP <-> HP: xscvdphp xscvhpdp
383 - Insert Exponent DP/QP: xsiexpdp xsiexpqp
392 - Extract Exponent/Significand DP/QP: xsxexpdp xsxsigdp xsxexpqp xsxsigqp
428 - Vector Insert Exponent DP/SP: xviexpdp xviexpsp
433 - Vector Extract Exponent/Significand DP/SP: xvxexpdp xvxexpsp xvxsigdp xvxsigsp
440 - Test Data Class SP/DP/QP: xststdcsp xststdcdp xststdcqp
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn32/
H A Ddcn32_resource.h281 SRI_ARR(DP_DB_CNTL, DP, id), SRI_ARR(DP_MSA_MISC, DP, id), \
282 SRI_ARR(DP_MSA_VBID_MISC, DP, id), SRI_ARR(DP_MSA_COLORIMETRY, DP, id), \
283 SRI_ARR(DP_MSA_TIMING_PARAM1, DP, id), \
284 SRI_ARR(DP_MSA_TIMING_PARAM2, DP, id), \
285 SRI_ARR(DP_MSA_TIMING_PARAM3, DP, id), \
286 SRI_ARR(DP_MSA_TIMING_PARAM4, DP, id), \
287 SRI_ARR(DP_MSE_RATE_CNTL, DP, id), SRI_ARR(DP_MSE_RATE_UPDATE, DP, id), \
288 SRI_ARR(DP_PIXEL_FORMAT, DP, id), SRI_ARR(DP_SEC_CNTL, DP, id), \
289 SRI_ARR(DP_SEC_CNTL1, DP, id), SRI_ARR(DP_SEC_CNTL2, DP, id), \
290 SRI_ARR(DP_SEC_CNTL5, DP, id), SRI_ARR(DP_SEC_CNTL6, DP, id), \
[all …]
/openbsd-src/gnu/llvm/llvm/include/llvm/IR/
H A DDiagnosticInfo.h131 virtual void print(DiagnosticPrinter &DP) const = 0;
177 void print(DiagnosticPrinter &DP) const override;
205 void print(DiagnosticPrinter &DP) const override;
227 void print(DiagnosticPrinter &DP) const override;
251 void print(DiagnosticPrinter &DP) const override;
281 void print(DiagnosticPrinter &DP) const override;
386 void print(DiagnosticPrinter &DP) const override;
470 void print(DiagnosticPrinter &DP) const override;
946 void print(DiagnosticPrinter &DP) const override;
965 void print(DiagnosticPrinter &DP) const override;
[all …]
/openbsd-src/sys/dev/pci/drm/amd/display/dc/dcn20/
H A Ddcn20_stream_encoder.h37 SRI(DP_DSC_CNTL, DP, id), \
38 SRI(DP_DSC_BYTES_PER_PIXEL, DP, id), \
40 SRI(DP_SEC_METADATA_TRANSMISSION, DP, id), \
42 SRI(DP_SEC_FRAMING4, DP, id)
/openbsd-src/gnu/usr.bin/gcc/gcc/testsuite/g++.old-deja/g++.jason/
H A Doverload17.C6 struct DP { struct
16 void h (DP p) in h()
/openbsd-src/gnu/llvm/llvm/lib/Transforms/Instrumentation/
H A DKCFI.cpp47 void print(DiagnosticPrinter &DP) const override { DP << Msg; } in print()
/openbsd-src/gnu/llvm/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.td38 def DP : Ri<13, "dp">, DwarfRegNum<[13]>;
56 R11, CP, DP, SP, LR)> {
/openbsd-src/gnu/llvm/llvm/lib/Linker/
H A DLinkDiagnosticInfo.h20 void print(DiagnosticPrinter &DP) const override;
/openbsd-src/gnu/llvm/llvm/lib/Analysis/
H A DLegacyDivergenceAnalysis.cpp326 DivergencePropagator DP(F, TTI, DT, PDT, DivergentValues, DivergentUses); in run() local
327 DP.populateWithSourcesOfDivergence(); in run()
328 DP.propagate(); in run()
/openbsd-src/gnu/usr.bin/binutils-2.17/include/opcode/
H A Dmaxq.h328 #define DP MODF /* For the module containig the data pointer registers. */ macro
526 "DP[0]", DP, 0x3, 0x30 | DP, Reg_16W, MAX},
528 "DP[1]", DP, 0x7, 0x70 | DP, Reg_16W, MAX},
/openbsd-src/regress/lib/libcrypto/x509/bettertls/certificates/
H A D2105.key15 czGlaBe5iHugbZGcUtqx+lxpZ4v/NJqJf7IiEHIeviQJ0ZScGWvxA1MCgYEAr+DP
H A D2996.key6 DP+Icktp6u53Bg6Lz1vjyjepJYZTuMWxrhDGY3p7/sK9zccl/UnPt8K6x0ZilOFg

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