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Searched refs:ADDL (Results 1 – 13 of 13) sorted by relevance

/openbsd-src/gnu/gcc/gcc/config/alpha/
H A Dev5.md130 ; than an ADDL instruction, which produced one of its operands, has a
132 ; later than the ADDL instruction, the latency is 9 (8 + 1).
/openbsd-src/gnu/usr.bin/gcc/gcc/config/alpha/
H A Dev5.md125 ; than an ADDL instruction, which produced one of its operands, has a
127 ; later than the ADDL instruction, the latency is 9 (8 + 1).
/openbsd-src/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64SchedTSV110.td608 def : InstRW<[TSV110Wr_4cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
610 def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
612 def : InstRW<[TSV110Wr_8cyc_1FSU1_1FSU2], (instregex "^[SU]?ADDL?Vv16i8v$")>;
H A DAArch64SchedA57.td369 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
371 def : InstRW<[A57Write_7cyc_1V_1X], (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
373 def : InstRW<[A57Write_8cyc_2X], (instregex "^[SU]?ADDL?Vv16i8v$")>;
H A DAArch64SchedAmpere1.td1036 (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v")>;
1041 (instregex "^[SU]?ADDL?V(v8i16|v4i32)v")>;
H A DAArch64SchedExynosM4.td734 def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Pv")>;
742 def : InstRW<[M4WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>;
H A DAArch64SchedExynosM5.td782 def : InstRW<[M5WriteNHAD3], (instregex "^[SU]?ADDL?Pv")>;
790 def : InstRW<[M5WriteNHAD3], (instregex "^[SU]?ADDL?Vv")>;
H A DAArch64SchedThunderX3T110.td1403 (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
1406 (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
1409 (instregex "^[SU]?ADDL?Vv16i8v$")>;
H A DAArch64SchedThunderX2T99.td1295 (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
1298 (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
1301 (instregex "^[SU]?ADDL?Vv16i8v$")>;
H A DAArch64SchedA64FX.td1420 (instregex "^[SU]?ADDL?V(v8i8|v4i16|v2i32)v$")>;
1423 (instregex "^[SU]?ADDL?V(v8i16|v4i32)v$")>;
1426 (instregex "^[SU]?ADDL?Vv16i8v$")>;
H A DAArch64SchedExynosM3.td612 def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Pv")>;
/openbsd-src/sys/arch/hppa/hppa/
H A Ddb_disasm.c557 #define ADDL 0x02, 0x50, 20, 7 /* ADD LOGICAL */ macro
1036 { ADDL, 0, "addl", addDasm },
/openbsd-src/gnu/usr.bin/gcc/gcc/
H A DChangeLog.612949 Reorganize. Handle ADDL like GR, add GR_AND_BR. Handle TFmode.