| /netbsd-src/sys/external/bsd/drm2/dist/drm/ |
| H A D | drm_rect.c | 216 int vscale = drm_calc_scale(src_h, dst_h); in drm_rect_calc_vscale() local 218 if (vscale < 0 || dst_h == 0) in drm_rect_calc_vscale() 219 return vscale; in drm_rect_calc_vscale() 221 if (vscale < min_vscale || vscale > max_vscale) in drm_rect_calc_vscale() 224 return vscale; in drm_rect_calc_vscale()
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| H A D | drm_atomic_helper.c | 779 int hscale, vscale; in drm_atomic_helper_check_plane_state() local 806 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale); in drm_atomic_helper_check_plane_state() 807 if (hscale < 0 || vscale < 0) { in drm_atomic_helper_check_plane_state()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| H A D | dvo_ns2501.c | 227 u16 vscale; /* vertical scaling factor, 10/11 */ member 254 .vscale = 40960 274 .vscale = 51232 293 .vscale = 65535 642 ns2501_writeb(dvo, NS2501_REG10, conf->vscale & 0xff); in ns2501_mode_set() 643 ns2501_writeb(dvo, NS2501_REG11, conf->vscale >> 8); in ns2501_mode_set()
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| H A D | intel_sprite.c | 394 int hscale, vscale; in skl_program_scaler() local 399 vscale = drm_rect_calc_vscale(&plane_state->uapi.src, in skl_program_scaler() 407 y_vphase = skl_scaler_calc_phase(1, vscale, false); in skl_program_scaler() 411 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false); in skl_program_scaler() 418 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); in skl_program_scaler()
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| H A D | intel_display.c | 6170 int pfit_w, pfit_h, hscale, vscale; in skl_pfit_enable() local 6180 vscale = (crtc_state->pipe_src_h << 16) / pfit_h; in skl_pfit_enable() 6183 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); in skl_pfit_enable()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | radeon_legacy_crtc.c | 62 bool hscale = true, vscale = true; in radeon_legacy_rmx_mode_set() local 121 vscale = false; in radeon_legacy_rmx_mode_set() 131 vscale = false; in radeon_legacy_rmx_mode_set() 149 if (!vscale) in radeon_legacy_rmx_mode_set()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | ExpandVectorPredication.cpp | 268 Intrinsic::getDeclaration(M, Intrinsic::vscale, Int32Ty); in discardEVLParameter()
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| H A D | CodeGenPrepare.cpp | 2229 case Intrinsic::vscale: { in optimizeCallInst()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/vim/syntax/ |
| H A D | llvm.vim | 215 syn keyword llvmConstant zeroinitializer undef null none poison vscale
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/ |
| H A D | LangRef.rst | 2048 This attribute indicates the minimum and maximum vscale value for the given 2051 assumptions are made about the range of vscale. 3423 < vscale x <# elements> x <elementtype> > ; Scalable vector 3428 elements is a constant multiple (called vscale) of the specified number 3429 of elements; vscale is a positive integer that is unknown at compile time 3445 | ``<vscale x 4 x i32>`` | Vector with a multiple of 4 32-bit integer values. | 9308 <result> = extractelement <vscale x n x <ty>> <val>, <ty2> <idx> ; yields <ty> 9352 …<result> = insertelement <vscale x n x <ty>> <val>, <ty> <elt>, <ty2> <idx> ; yields <vscale x n x… 9397 …<result> = shufflevector <vscale x n x <ty>> <v1>, <vscale x n x <ty>> v2, <vscale x m x i32> <mas… 16798 …declare <vscale x 4 x float> @llvm.experimental.vector.insert.v4f32(<vscale x 4 x float> %vec, <4 … [all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64SVEInstrInfo.td | 1671 def : Pat<(vscale GPR64:$scale), (MADDXrrr (UBFMXri (RDVLI_XI 1), 4, 63), $scale, XZR)>; 1674 def : Pat<(vscale (i64 1)), (UBFMXri (RDVLI_XI 1), 4, 63)>; 1675 def : Pat<(vscale (i64 -1)), (SBFMXri (RDVLI_XI -1), 4, 63)>; 1677 def : Pat<(vscale (sve_rdvl_imm i32:$imm)), (RDVLI_XI $imm)>; 1678 def : Pat<(vscale (sve_cnth_imm i32:$imm)), (CNTH_XPiI 31, $imm)>; 1679 def : Pat<(vscale (sve_cntw_imm i32:$imm)), (CNTW_XPiI 31, $imm)>; 1680 def : Pat<(vscale (sve_cntd_imm i32:$imm)), (CNTD_XPiI 31, $imm)>; 1682 def : Pat<(vscale (sve_cnth_imm_neg i32:$imm)), (SUBXrs XZR, (CNTH_XPiI 31, $imm), 0)>; 1683 def : Pat<(vscale (sve_cntw_imm_neg i32:$imm)), (SUBXrs XZR, (CNTW_XPiI 31, $imm), 0)>; 1684 def : Pat<(vscale (sve_cntd_imm_neg i32:$imm)), (SUBXrs XZR, (CNTD_XPiI 31, $imm), 0)>; [all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| H A D | Attributes.td | 253 /// Minimum/Maximum vscale value for function.
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| H A D | PatternMatch.h | 2436 if (m_Intrinsic<Intrinsic::vscale>().match(V))
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/AsmParser/ |
| H A D | LLLexer.cpp | 730 KEYWORD(vscale); in LexIdentifier()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.td | 276 // thus `vscale` can be defined as VLEN/64,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/IR/ |
| H A D | IRBuilder.cpp | 89 Intrinsic::getDeclaration(M, Intrinsic::vscale, {Scaling->getType()}); in CreateVScale()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 334 def vscale : SDNode<"ISD::VSCALE" , SDTIntUnaryOp, []>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 5773 case Intrinsic::vscale: { in visitIntrinsicCall()
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 9114 Function *F = CGM.getIntrinsic(Intrinsic::vscale, Ty); in EmitAArch64SVEBuiltinExpr()
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