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Searched refs:reg_offset (Results 1 – 25 of 124) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_arct_reg_init.c39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in arct_reg_base_init()
40 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in arct_reg_base_init()
41 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in arct_reg_base_init()
42 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in arct_reg_base_init()
43 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); in arct_reg_base_init()
44 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in arct_reg_base_init()
45 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in arct_reg_base_init()
46 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in arct_reg_base_init()
47 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in arct_reg_base_init()
48 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); in arct_reg_base_init()
[all …]
H A Damdgpu_navi14_reg_init.c39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); in navi14_reg_base_init()
40 adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i])); in navi14_reg_base_init()
41 adev->reg_offset[MMHUB_HWIP][i] = (const uint32_t *)(&(MMHUB_BASE.instance[i])); in navi14_reg_base_init()
42 adev->reg_offset[ATHUB_HWIP][i] = (const uint32_t *)(&(ATHUB_BASE.instance[i])); in navi14_reg_base_init()
43 adev->reg_offset[NBIO_HWIP][i] = (const uint32_t *)(&(NBIF0_BASE.instance[i])); in navi14_reg_base_init()
44 adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i])); in navi14_reg_base_init()
45 adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i])); in navi14_reg_base_init()
46 adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(UVD0_BASE.instance[i])); in navi14_reg_base_init()
47 adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i])); in navi14_reg_base_init()
48 adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DMU_BASE.instance[i])); in navi14_reg_base_init()
[all …]
H A Damdgpu_navi10_reg_init.c39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); in navi10_reg_base_init()
40 adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i])); in navi10_reg_base_init()
41 adev->reg_offset[MMHUB_HWIP][i] = (const uint32_t *)(&(MMHUB_BASE.instance[i])); in navi10_reg_base_init()
42 adev->reg_offset[ATHUB_HWIP][i] = (const uint32_t *)(&(ATHUB_BASE.instance[i])); in navi10_reg_base_init()
43 adev->reg_offset[NBIO_HWIP][i] = (const uint32_t *)(&(NBIO_BASE.instance[i])); in navi10_reg_base_init()
44 adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i])); in navi10_reg_base_init()
45 adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i])); in navi10_reg_base_init()
46 adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(VCN_BASE.instance[i])); in navi10_reg_base_init()
47 adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i])); in navi10_reg_base_init()
48 adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DCN_BASE.instance[i])); in navi10_reg_base_init()
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H A Damdgpu_navi12_reg_init.c39 adev->reg_offset[GC_HWIP][i] = (const uint32_t *)(&(GC_BASE.instance[i])); in navi12_reg_base_init()
40 adev->reg_offset[HDP_HWIP][i] = (const uint32_t *)(&(HDP_BASE.instance[i])); in navi12_reg_base_init()
41 adev->reg_offset[MMHUB_HWIP][i] = (const uint32_t *)(&(MMHUB_BASE.instance[i])); in navi12_reg_base_init()
42 adev->reg_offset[ATHUB_HWIP][i] = (const uint32_t *)(&(ATHUB_BASE.instance[i])); in navi12_reg_base_init()
43 adev->reg_offset[NBIO_HWIP][i] = (const uint32_t *)(&(NBIF0_BASE.instance[i])); in navi12_reg_base_init()
44 adev->reg_offset[MP0_HWIP][i] = (const uint32_t *)(&(MP0_BASE.instance[i])); in navi12_reg_base_init()
45 adev->reg_offset[MP1_HWIP][i] = (const uint32_t *)(&(MP1_BASE.instance[i])); in navi12_reg_base_init()
46 adev->reg_offset[VCN_HWIP][i] = (const uint32_t *)(&(UVD0_BASE.instance[i])); in navi12_reg_base_init()
47 adev->reg_offset[DF_HWIP][i] = (const uint32_t *)(&(DF_BASE.instance[i])); in navi12_reg_base_init()
48 adev->reg_offset[DCE_HWIP][i] = (const uint32_t *)(&(DMU_BASE.instance[i])); in navi12_reg_base_init()
[all …]
H A Damdgpu_vega10_reg_init.c39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega10_reg_base_init()
40 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega10_reg_base_init()
41 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
42 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega10_reg_base_init()
43 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega10_reg_base_init()
44 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
45 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
46 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega10_reg_base_init()
47 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega10_reg_base_init()
48 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); in vega10_reg_base_init()
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H A Dsoc15_common.h30 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
33 WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
34 (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
38 RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
41 RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
44 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
47 WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
50 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
55 uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
64 tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
[all …]
H A Damdgpu_jpeg_v1_0.c41 …_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) in jpeg_v1_0_decode_ring_patch_wreg() argument
45 if (((reg_offset >= 0x1f800) && (reg_offset <= 0x21fff)) || in jpeg_v1_0_decode_ring_patch_wreg()
46 ((reg_offset >= 0x1e000) && (reg_offset <= 0x1e1ff))) { in jpeg_v1_0_decode_ring_patch_wreg()
48 ring->ring[(*ptr)++] = PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0); in jpeg_v1_0_decode_ring_patch_wreg()
50 ring->ring[(*ptr)++] = reg_offset; in jpeg_v1_0_decode_ring_patch_wreg()
60 uint32_t reg, reg_offset, val, mask, i; in jpeg_v1_0_decode_ring_set_patch_ring() local
64 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
66 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); in jpeg_v1_0_decode_ring_set_patch_ring()
70 reg_offset = (reg << 2); in jpeg_v1_0_decode_ring_set_patch_ring()
72 jpeg_v1_0_decode_ring_patch_wreg(ring, &ptr, reg_offset, val); in jpeg_v1_0_decode_ring_set_patch_ring()
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H A Damdgpu_vega20_reg_init.c39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in vega20_reg_base_init()
40 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega20_reg_base_init()
41 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
42 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); in vega20_reg_base_init()
43 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
44 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
45 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
46 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega20_reg_base_init()
47 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); in vega20_reg_base_init()
48 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in vega20_reg_base_init()
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H A Dmmsch_v1_0.h65 uint32_t reg_offset : 28; member
70 uint32_t reg_offset : 20; member
103 uint32_t reg_offset, in mmsch_v1_0_insert_direct_wt() argument
106 direct_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_wt()
113 uint32_t reg_offset, in mmsch_v1_0_insert_direct_rd_mod_wt() argument
116 direct_rd_mod_wt->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_rd_mod_wt()
125 uint32_t reg_offset, in mmsch_v1_0_insert_direct_poll() argument
128 direct_poll->cmd_header.reg_offset = reg_offset; in mmsch_v1_0_insert_direct_poll()
H A Dsoc15.h51 uint32_t reg_offset; member
61 uint32_t reg_offset; member
70 uint32_t reg_offset; member
79 …define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.…
H A Damdgpu_gfx_v8_0.c2104 u32 reg_offset; in gfx_v8_0_tiling_mode_table_init() local
2109 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2110 modearray[reg_offset] = 0; in gfx_v8_0_tiling_mode_table_init()
2112 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2113 mod2array[reg_offset] = 0; in gfx_v8_0_tiling_mode_table_init()
2277 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
2278 if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && in gfx_v8_0_tiling_mode_table_init()
2279 reg_offset != 23) in gfx_v8_0_tiling_mode_table_init()
2280 WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset]); in gfx_v8_0_tiling_mode_table_init()
2282 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) in gfx_v8_0_tiling_mode_table_init()
[all …]
H A Damdgpu_jpeg_v2_0.c605 uint32_t reg_offset = (reg << 2); in jpeg_v2_0_dec_ring_emit_reg_wait() local
617 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { in jpeg_v2_0_dec_ring_emit_reg_wait()
620 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3)); in jpeg_v2_0_dec_ring_emit_reg_wait()
622 amdgpu_ring_write(ring, reg_offset); in jpeg_v2_0_dec_ring_emit_reg_wait()
646 uint32_t reg_offset = (reg << 2); in jpeg_v2_0_dec_ring_emit_wreg() local
650 if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) { in jpeg_v2_0_dec_ring_emit_wreg()
653 PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0)); in jpeg_v2_0_dec_ring_emit_wreg()
655 amdgpu_ring_write(ring, reg_offset); in jpeg_v2_0_dec_ring_emit_wreg()
H A Damdgpu_nv.c216 u32 sh_num, u32 reg_offset) in nv_read_indexed_register() argument
224 val = RREG32(reg_offset); in nv_read_indexed_register()
234 u32 sh_num, u32 reg_offset) in nv_get_register_value() argument
237 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
239 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) in nv_get_register_value()
241 return RREG32(reg_offset); in nv_get_register_value()
246 u32 sh_num, u32 reg_offset, u32 *value) in nv_read_register() argument
254 if (reg_offset != in nv_read_register()
255 (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset)) in nv_read_register()
260 se_num, sh_num, reg_offset); in nv_read_register()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_cik_sdma.c257 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local
266 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_gfx_stop()
268 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_stop()
269 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); in cik_sdma_gfx_stop()
271 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_stop()
272 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0); in cik_sdma_gfx_stop()
311 uint32_t reg_offset, value; in cik_sdma_ctx_switch_enable() local
316 reg_offset = SDMA0_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
318 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()
319 value = RREG32(SDMA0_CNTL + reg_offset); in cik_sdma_ctx_switch_enable()
[all …]
H A Dradeon_ni_dma.c197 u32 reg_offset, wb_offset; in cayman_dma_resume() local
203 reg_offset = DMA0_REGISTER_OFFSET; in cayman_dma_resume()
207 reg_offset = DMA1_REGISTER_OFFSET; in cayman_dma_resume()
211 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); in cayman_dma_resume()
212 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); in cayman_dma_resume()
220 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume()
223 WREG32(DMA_RB_RPTR + reg_offset, 0); in cayman_dma_resume()
224 WREG32(DMA_RB_WPTR + reg_offset, 0); in cayman_dma_resume()
227 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset, in cayman_dma_resume()
229 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset, in cayman_dma_resume()
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/netbsd-src/sys/dev/isa/
H A Dnca_isa.c123 nca_isa_test(bus_space_tag_t iot, bus_space_handle_t ioh, bus_size_t reg_offset) in nca_isa_test() argument
127 bus_space_write_1(iot, ioh, reg_offset + C80_ICR, SCI_ICMD_RST); in nca_isa_test()
128 bus_space_write_1(iot, ioh, reg_offset + C80_ODR, 0); in nca_isa_test()
132 if (bus_space_read_1(iot, ioh, reg_offset + C80_CSBR) != SCI_BUS_RST) { in nca_isa_test()
135 __func__, bus_space_read_1(iot, ioh, reg_offset+C80_CSBR)); in nca_isa_test()
137 bus_space_write_1(iot, ioh, reg_offset+C80_ICR, 0); in nca_isa_test()
141 bus_space_write_1(iot, ioh, reg_offset + C80_ICR, 0); in nca_isa_test()
146 bus_space_read_1(iot, ioh, reg_offset + C80_RPIR); in nca_isa_test()
150 if (bus_space_read_1(iot, ioh, reg_offset + C80_BSR) & (SCI_CSR_PERR | in nca_isa_test()
154 __func__, bus_space_read_1(iot, ioh, reg_offset+C80_BSR)); in nca_isa_test()
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/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/nds32/
H A Dnds32.h184 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \ argument
187 ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \
188 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \
189 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
191 #define NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG(reg_offset, mode, type) \ argument
194 ? (((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM + 1) & ~1) \
195 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM)) \
196 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))
200 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type) \ argument
201 ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
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/netbsd-src/external/gpl3/gcc/dist/gcc/config/nds32/
H A Dnds32.h184 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \ argument
187 ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \
188 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \
189 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
191 #define NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG(reg_offset, mode, type) \ argument
194 ? (((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM + 1) & ~1) \
195 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM)) \
196 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))
200 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type) \ argument
201 ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
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/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/i386/
H A Dwinnt.c854 HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; member
938 if (seh->reg_offset[regno] > 0 && seh->reg_offset[regno] <= alloc_offset) in i386_pe_seh_cold_init()
948 alloc_offset - seh->reg_offset[regno]); in i386_pe_seh_cold_init()
970 if (seh->reg_offset[regno] > alloc_offset) in i386_pe_seh_cold_init()
980 seh->sp_offset - seh->reg_offset[regno]); in i386_pe_seh_cold_init()
1016 seh->reg_offset[regno] = seh->sp_offset; in seh_emit_push()
1034 seh->reg_offset[regno] = cfa_offset; in seh_emit_save()
1075 HOST_WIDE_INT reg_offset = 0; in seh_cfa_adjust_cfa() local
1083 reg_offset = INTVAL (XEXP (src, 1)); in seh_cfa_adjust_cfa()
1088 reg_offset = -INTVAL (XEXP (src, 1)); in seh_cfa_adjust_cfa()
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/i386/
H A Dwinnt.cc853 HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; member
937 if (seh->reg_offset[regno] > 0 && seh->reg_offset[regno] <= alloc_offset) in i386_pe_seh_cold_init()
947 alloc_offset - seh->reg_offset[regno]); in i386_pe_seh_cold_init()
969 if (seh->reg_offset[regno] > alloc_offset) in i386_pe_seh_cold_init()
979 seh->sp_offset - seh->reg_offset[regno]); in i386_pe_seh_cold_init()
1015 seh->reg_offset[regno] = seh->sp_offset; in seh_emit_push()
1033 seh->reg_offset[regno] = cfa_offset; in seh_emit_save()
1074 HOST_WIDE_INT reg_offset = 0; in seh_cfa_adjust_cfa() local
1082 reg_offset = INTVAL (XEXP (src, 1)); in seh_cfa_adjust_cfa()
1087 reg_offset = -INTVAL (XEXP (src, 1)); in seh_cfa_adjust_cfa()
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/mips/
H A Dlinux-unwind.h51 _Unwind_Ptr new_cfa, reg_offset; in mips_fallback_frame_state() local
100 reg_offset = 4; in mips_fallback_frame_state()
102 reg_offset = 0; in mips_fallback_frame_state()
108 = (_Unwind_Ptr)&(sc->sc_regs[i]) + reg_offset - new_cfa; in mips_fallback_frame_state()
/netbsd-src/external/gpl3/gcc/dist/libgcc/config/mips/
H A Dlinux-unwind.h51 _Unwind_Ptr new_cfa, reg_offset; in mips_fallback_frame_state() local
100 reg_offset = 4; in mips_fallback_frame_state()
102 reg_offset = 0; in mips_fallback_frame_state()
108 = (_Unwind_Ptr)&(sc->sc_regs[i]) + reg_offset - new_cfa; in mips_fallback_frame_state()
/netbsd-src/external/gpl3/gcc/dist/gcc/config/or1k/
H A Dor1k.cc214 HOST_WIDE_INT reg_offset, this_offset; in or1k_expand_prologue() local
226 reg_offset = (sp_offset + cfun->machine->local_vars_size in or1k_expand_prologue()
229 reg_offset -= this_offset; in or1k_expand_prologue()
242 or1k_save_reg (regno, reg_offset); in or1k_expand_prologue()
243 reg_offset += UNITS_PER_WORD; in or1k_expand_prologue()
249 or1k_save_reg (HARD_FRAME_POINTER_REGNUM, reg_offset); in or1k_expand_prologue()
257 reg_offset += UNITS_PER_WORD; in or1k_expand_prologue()
263 or1k_save_reg (LR_REGNUM, reg_offset); in or1k_expand_prologue()
264 reg_offset += UNITS_PER_WORD; in or1k_expand_prologue()
266 gcc_assert (reg_offset + this_offset == 0); in or1k_expand_prologue()
[all …]
/netbsd-src/usr.bin/scmdctl/
H A Dcommon.c221 uint8_t reg, reg_index = 0, reg_offset = 0; in common_invert_motor() local
241 reg_offset = motor_index / 8; in common_invert_motor()
244 reg = SCMD_REG_INV_2_9 + reg_offset; in common_invert_motor()
246 …_index: %d ; reg_offset: %d ; reg_index: %02X ; reg: %02X\n",motor_index,reg_offset,reg_index,reg); in common_invert_motor()
263 uint8_t reg, reg_index = 0, reg_offset = 0; in common_bridge_motor() local
276 reg_offset = module_index / 8; in common_bridge_motor()
279 reg = SCMD_REG_BRIDGE_SLV_L + reg_offset; in common_bridge_motor()
281 …index: %d ; reg_offset: %d ; reg_index: %02X ; reg: %02X\n",module_index,reg_offset,reg_index,reg); in common_bridge_motor()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_common_baco.c97 reg = entry[i].reg_offset; in baco_program_registers()
117 reg = adev->reg_offset[entry[i].hwip][entry[i].inst][entry[i].seg] in soc15_baco_program_registers()
118 + entry[i].reg_offset; in soc15_baco_program_registers()

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