Searched refs:reference_divider (Results 1 – 13 of 13) sorted by relevance
57 u32 reference_divider, post_divider; in rv730_populate_sclk_value() local66 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()74 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()101 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv730_populate_sclk_value()136 u32 post_divider, reference_divider; in rv730_populate_mclk_value() local144 reference_divider = dividers.ref_div + 1; in rv730_populate_mclk_value()177 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv730_populate_mclk_value()
137 u32 reference_divider; in rv740_populate_sclk_value() local146 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()148 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()169 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv740_populate_sclk_value()
329 u32 post_divider, reference_divider, feedback_divider8; in rv770_calculate_fractional_mpll_feedback_divider() local338 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()341 (8 * fyclk * reference_divider * post_divider) / reference_clock; in rv770_calculate_fractional_mpll_feedback_divider()506 u32 reference_divider, post_divider; in rv770_populate_sclk_value() local515 reference_divider = 1 + dividers.ref_div; in rv770_populate_sclk_value()522 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()548 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in rv770_populate_sclk_value()
2017 u32 reference_divider; in ni_calculate_sclk_params() local2026 reference_divider = 1 + dividers.ref_div; in ni_calculate_sclk_params()2029 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()2050 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ni_calculate_sclk_params()
4800 u32 reference_divider; in si_calculate_sclk_params() local4809 reference_divider = 1 + dividers.ref_div; in si_calculate_sclk_params()4811 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()4832 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in si_calculate_sclk_params()
3176 u32 reference_divider; in ci_calculate_sclk_params() local3186 reference_divider = 1 + dividers.ref_div; in ci_calculate_sclk_params()3199 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in ci_calculate_sclk_params()
242 pll_settings->reference_divider = ref_divider; in calc_fb_divider_checking_tolerance()342 if (pll_settings->reference_divider) { in calculate_pixel_clock_pll_dividers()343 min_ref_divider = pll_settings->reference_divider; in calculate_pixel_clock_pll_dividers()344 max_ref_divider = pll_settings->reference_divider; in calculate_pixel_clock_pll_dividers()457 pll_settings->reference_divider = in pll_adjust_pix_clk()458 bp_adjust_pixel_clock_params.reference_divider; in pll_adjust_pix_clk()701 pll_settings->reference_divider * ss_data->modulation_freq_hz); in calculate_ss()870 bp_pc_params.reference_divider = pll_settings->reference_divider; in dce110_program_pix_clk()
202 uint32_t reference_divider; member219 uint32_t reference_divider; member
114 uint32_t reference_divider; member
962 cpu_to_le16((uint16_t)bp_params->reference_divider); in set_pixel_clock_v3()1033 (uint8_t)(bp_params->reference_divider); in set_pixel_clock_v5()1109 (uint8_t) bp_params->reference_divider; in set_pixel_clock_v6()1525 bp_params->reference_divider = params.sOutput.ucRefDiv; in adjust_display_pll_v3()
811 uint32_t reference_divider; in iceland_calculate_sclk_params() local824 reference_divider = 1 + dividers.uc_pll_ref_div; in iceland_calculate_sclk_params()854 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); in iceland_calculate_sclk_params()
554 uint32_t reference_divider; in tonga_calculate_sclk_params() local567 reference_divider = 1 + dividers.uc_pll_ref_div; in tonga_calculate_sclk_params()597 uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); in tonga_calculate_sclk_params()
5264 u32 reference_divider; in si_calculate_sclk_params() local5273 reference_divider = 1 + dividers.ref_div; in si_calculate_sclk_params()5275 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()5296 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); in si_calculate_sclk_params()