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Searched refs:pipe_offset (Results 1 – 10 of 10) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/
H A Damdgpu_irq_service_dce110.c217 uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; in dce110_vblank_set() local
220 dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; in dce110_vblank_set()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/
H A Dkfd_device_queue_manager.c80 int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec in is_pipe_enabled() local
85 if (test_bit(pipe_offset + i, in is_pipe_enabled()
912 int pipe_offset = pipe * get_queues_per_pipe(dqm); in initialize_nocpsch() local
915 if (test_bit(pipe_offset + queue, in initialize_nocpsch()
1983 int pipe_offset = pipe * get_queues_per_pipe(dqm); in dqm_debugfs_hqds() local
1986 if (!test_bit(pipe_offset + queue, in dqm_debugfs_hqds()
/netbsd-src/external/bsd/tmux/dist/
H A Dcmd-pipe-pane.c64 struct window_pane_offset *wpo = &wp->pipe_offset; in cmd_pipe_pane_exec()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_evergreen.c1834 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in evergreen_line_buffer_adjust() local
1875 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in evergreen_line_buffer_adjust()
1878 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in evergreen_line_buffer_adjust()
2170 u32 pipe_offset = radeon_crtc->crtc_id * 16; in evergreen_program_watermarks() local
2289 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2293 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2294 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
2298 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2301 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2302 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
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H A Dradeon_si.c1984 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce6_line_buffer_adjust() local
2014 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce6_line_buffer_adjust()
2017 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce6_line_buffer_adjust()
H A Dradeon_cik.c8888 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce8_line_buffer_adjust() local
8920 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce8_line_buffer_adjust()
8923 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce8_line_buffer_adjust()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_dce_v10_0.c604 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v10_0_line_buffer_adjust() local
637 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v10_0_line_buffer_adjust()
639 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); in dce_v10_0_line_buffer_adjust()
642 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v10_0_line_buffer_adjust()
H A Damdgpu_dce_v11_0.c630 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v11_0_line_buffer_adjust() local
663 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v11_0_line_buffer_adjust()
665 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); in dce_v11_0_line_buffer_adjust()
668 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v11_0_line_buffer_adjust()
H A Damdgpu_dce_v8_0.c541 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; in dce_v8_0_line_buffer_adjust() local
574 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce_v8_0_line_buffer_adjust()
577 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce_v8_0_line_buffer_adjust()
H A Damdgpu_dce_v6_0.c1000 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; in dce_v6_0_line_buffer_adjust() local
1030 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce_v6_0_line_buffer_adjust()
1033 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce_v6_0_line_buffer_adjust()