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Searched refs:phy (Results 1 – 25 of 1610) sorted by relevance

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/netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb135_board.dtsi212 phy0: ethernet-phy@0 {
215 phy1: ethernet-phy@1 {
218 phy2: ethernet-phy@2 {
221 phy3: ethernet-phy@3 {
224 phy4: ethernet-phy@4 {
227 phy5: ethernet-phy@5 {
230 phy6: ethernet-phy@6 {
233 phy7: ethernet-phy@7 {
236 phy8: ethernet-phy@8 {
239 phy9: ethernet-phy@9 {
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_combo_phy.c51 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in cnl_get_procmon_ref_values() argument
56 val = I915_READ(ICL_PORT_COMP_DW3(phy)); in cnl_get_procmon_ref_values()
82 enum phy phy) in cnl_set_procmon_ref_values() argument
87 procmon = cnl_get_procmon_ref_values(dev_priv, phy); in cnl_set_procmon_ref_values()
89 val = I915_READ(ICL_PORT_COMP_DW1(phy)); in cnl_set_procmon_ref_values()
92 I915_WRITE(ICL_PORT_COMP_DW1(phy), val); in cnl_set_procmon_ref_values()
94 I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9); in cnl_set_procmon_ref_values()
95 I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10); in cnl_set_procmon_ref_values()
99 enum phy phy, i915_reg_t reg, u32 mask, in check_phy_reg() argument
107 phy_name(phy), in check_phy_reg()
[all …]
H A Dintel_dpio_phy.c233 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy) in bxt_get_phy_info() argument
239 return &phy_list[phy]; in bxt_get_phy_info()
243 enum dpio_phy *phy, enum dpio_channel *ch) in bxt_port_to_phy_channel() argument
254 *phy = i; in bxt_port_to_phy_channel()
261 *phy = i; in bxt_port_to_phy_channel()
268 *phy = DPIO_PHY0; in bxt_port_to_phy_channel()
277 enum dpio_phy phy; in bxt_ddi_phy_set_signal_level() local
280 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); in bxt_ddi_phy_set_signal_level()
286 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
288 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
[all …]
/netbsd-src/sys/dev/pci/igc/
H A Digc_phy.c24 struct igc_phy_info *phy = &hw->phy; in igc_init_phy_ops_generic() local
28 phy->ops.init_params = igc_null_ops_generic; in igc_init_phy_ops_generic()
29 phy->ops.acquire = igc_null_ops_generic; in igc_init_phy_ops_generic()
30 phy->ops.check_reset_block = igc_null_ops_generic; in igc_init_phy_ops_generic()
31 phy->ops.force_speed_duplex = igc_null_ops_generic; in igc_init_phy_ops_generic()
32 phy->ops.get_info = igc_null_ops_generic; in igc_init_phy_ops_generic()
33 phy->ops.set_page = igc_null_set_page; in igc_init_phy_ops_generic()
34 phy->ops.read_reg = igc_null_read_reg; in igc_init_phy_ops_generic()
35 phy->ops.read_reg_locked = igc_null_read_reg; in igc_init_phy_ops_generic()
36 phy->ops.read_reg_page = igc_null_read_reg; in igc_init_phy_ops_generic()
[all …]
/netbsd-src/sys/dev/pci/cxgb/
H A Dcxgb_ael1002.c51 static void ael100x_txon(struct cphy *phy) in ael100x_txon() argument
53 int tx_on_gpio = phy->addr == 0 ? F_GPIO7_OUT_VAL : F_GPIO2_OUT_VAL; in ael100x_txon()
56 t3_set_reg_field(phy->adapter, A_T3DBG_GPIO_EN, 0, tx_on_gpio); in ael100x_txon()
60 static int ael1002_power_down(struct cphy *phy, int enable) in ael1002_power_down() argument
64 err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_DISABLE, !!enable); in ael1002_power_down()
66 err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR, in ael1002_power_down()
71 static int ael1002_reset(struct cphy *phy, int wait) in ael1002_reset() argument
75 if ((err = ael1002_power_down(phy, 0)) || in ael1002_reset()
76 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_CONFIG1, 1)) || in ael1002_reset()
77 (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_HI, 0)) || in ael1002_reset()
[all …]
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
H A Dfsl-ls2088a-rdb.dts27 phy-handle = <&mdio1_phy1>;
28 phy-connection-type = "10gbase-r";
32 phy-handle = <&mdio1_phy2>;
33 phy-connection-type = "10gbase-r";
37 phy-handle = <&mdio1_phy3>;
38 phy-connection-type = "10gbase-r";
42 phy-handle = <&mdio1_phy4>;
43 phy-connection-type = "10gbase-r";
47 phy-handle = <&mdio2_phy1>;
48 phy-connection-type = "10gbase-r";
[all …]
H A Dfsl-ls1088a-rdb.dts21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
34 phy-handle = <&mdio1_phy6>;
35 phy-connection-type = "qsgmii";
41 phy-handle = <&mdio1_phy7>;
42 phy-connection-type = "qsgmii";
48 phy-handle = <&mdio1_phy8>;
49 phy-connection-type = "qsgmii";
[all …]
H A Dfsl-ls1043a-rdb.dts128 phy-handle = <&qsgmii_phy1>;
129 phy-connection-type = "qsgmii";
133 phy-handle = <&qsgmii_phy2>;
134 phy-connection-type = "qsgmii";
138 phy-handle = <&rgmii_phy1>;
139 phy-connection-type = "rgmii-id";
143 phy-handle = <&rgmii_phy2>;
144 phy-connection-type = "rgmii-id";
148 phy-handle = <&qsgmii_phy3>;
149 phy-connection-type = "qsgmii";
[all …]
H A Dfsl-ls1046a-rdb.dts131 phy-handle = <&rgmii_phy1>;
132 phy-connection-type = "rgmii-id";
136 phy-handle = <&rgmii_phy2>;
137 phy-connection-type = "rgmii-id";
141 phy-handle = <&sgmii_phy1>;
142 phy-connection-type = "sgmii";
146 phy-handle = <&sgmii_phy2>;
147 phy-connection-type = "sgmii";
151 phy-handle = <&aqr106_phy>;
152 phy-connection-type = "xgmii";
[all …]
H A Dfsl-ls1088a-ten64.dts98 phy-connection-type = "10gbase-r";
106 phy-connection-type = "10gbase-r";
112 phy-handle = <&mdio1_phy5>;
113 phy-connection-type = "qsgmii";
119 phy-handle = <&mdio1_phy6>;
120 phy-connection-type = "qsgmii";
126 phy-handle = <&mdio1_phy7>;
127 phy-connection-type = "qsgmii";
133 phy-handle = <&mdio1_phy8>;
134 phy-connection-type = "qsgmii";
[all …]
/netbsd-src/sys/dev/pci/ixgbe/
H A Dixgbe_phy.c120 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_read_i2c_combined_generic_int()
197 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_write_i2c_combined_generic_int()
257 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_phy_ops_generic() local
262 phy->ops.identify = ixgbe_identify_phy_generic; in ixgbe_init_phy_ops_generic()
263 phy->ops.reset = ixgbe_reset_phy_generic; in ixgbe_init_phy_ops_generic()
264 phy->ops.read_reg = ixgbe_read_phy_reg_generic; in ixgbe_init_phy_ops_generic()
265 phy->ops.write_reg = ixgbe_write_phy_reg_generic; in ixgbe_init_phy_ops_generic()
266 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; in ixgbe_init_phy_ops_generic()
267 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; in ixgbe_init_phy_ops_generic()
268 phy->ops.setup_link = ixgbe_setup_phy_link_generic; in ixgbe_init_phy_ops_generic()
[all …]
H A Dixgbe_x550.c262 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_check_cs4227()
364 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | in ixgbe_read_phy_reg_mdi_22()
414 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | in ixgbe_write_phy_reg_mdi_22()
465 hw->phy.type = ixgbe_phy_x550em_kx4; in ixgbe_identify_phy_x550em()
468 hw->phy.type = ixgbe_phy_x550em_xfi; in ixgbe_identify_phy_x550em()
473 hw->phy.type = ixgbe_phy_x550em_kr; in ixgbe_identify_phy_x550em()
479 hw->phy.type = ixgbe_phy_ext_1g_t; in ixgbe_identify_phy_x550em()
483 hw->phy.type = ixgbe_phy_fw; in ixgbe_identify_phy_x550em()
485 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM; in ixgbe_identify_phy_x550em()
487 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM; in ixgbe_identify_phy_x550em()
[all …]
/netbsd-src/sys/rump/dev/lib/libmiiphy/
H A DMIIPHY.ioconf4 ioconf phy
10 acphy* at mii? phy ? # Altima AC101 and AMD Am79c874 PHYs
11 amhphy* at mii? phy ? # AMD 79c901 Ethernet PHYs
12 atphy* at mii? phy ? # Attansic/Atheros PHYs
13 bmtphy* at mii? phy ? # Broadcom BCM5201 and BCM5202 PHYs
14 brgphy* at mii? phy ? # Broadcom BCM5400-family PHYs
15 ciphy* at mii? phy ? # Cicada CS8201 Gig-E PHYs
16 dmphy* at mii? phy ? # Davicom DM9101 PHYs
17 etphy* at mii? phy ? # Agere/LSI ET1011 TruePHY Gig-E PHYs
18 exphy* at mii? phy ? # 3Com internal PHYs
[all …]
/netbsd-src/sys/arch/arm/sunxi/
H A Dsunxi_usb3phy.c91 #define PHY_READ(phy, reg) \ argument
92 bus_space_read_4((phy)->phy_bst, (phy)->phy_bsh, (reg))
93 #define PHY_WRITE(phy, reg, val) \ argument
94 bus_space_write_4((phy)->phy_bst, (phy)->phy_bsh, (reg), (val))
115 struct sunxi_usb3phy * const phy = priv; in sunxi_usb3phy_enable() local
119 val = PHY_READ(phy, SUNXI_PHY_EXTERNAL_CONTROL); in sunxi_usb3phy_enable()
123 PHY_WRITE(phy, SUNXI_PHY_EXTERNAL_CONTROL, val); in sunxi_usb3phy_enable()
125 val = PHY_READ(phy, SUNXI_PIPE_CLOCK_CONTROL); in sunxi_usb3phy_enable()
127 PHY_WRITE(phy, SUNXI_PIPE_CLOCK_CONTROL, val); in sunxi_usb3phy_enable()
129 val = PHY_READ(phy, SUNXI_APP); in sunxi_usb3phy_enable()
[all …]
/netbsd-src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/mscc/
H A Docelot_pcb120.dts8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
45 phy7: ethernet-phy@0 {
51 phy6: ethernet-phy@1 {
57 phy5: ethernet-phy@2 {
63 phy4: ethernet-phy@3 {
73 phy-handle = <&phy0>;
74 phy-mode = "internal";
79 phy-handle = <&phy1>;
80 phy-mode = "internal";
85 phy-handle = <&phy2>;
[all …]
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/marvell/
H A Darmada-8040-db.dts52 cp0_usb3_0_phy: cp0-usb3-0-phy {
66 cp1_usb3_0_phy: cp1-usb3-0-phy {
107 phy-names = "cp0-pcie0-x1-phy";
114 phy-names = "cp0-pcie2-x1-phy";
148 phy-names = "cp0-sata0-0-phy";
152 phy-names = "cp0-sata0-1-phy";
162 usb-phy = <&cp0_usb3_0_phy>;
164 phy-names = "utmi";
172 phy-supply = <&cp0_reg_usb3_1_vbus>;
179 phy-names = "usb", "utmi";
[all …]
H A Darmada-3720-turris-mox.dts167 phy-mode = "rgmii-id";
168 phy-handle = <&phy1>;
173 phy-mode = "2500base-x";
279 phy-supply = <&exp_usb3_vbus>;
293 phy1: ethernet-phy@1 {
350 phy-handle = <&switch0phy1>;
356 phy-handle = <&switch0phy2>;
362 phy-handle = <&switch0phy3>;
368 phy-handle = <&switch0phy4>;
374 phy-handle = <&switch0phy5>;
[all …]
/netbsd-src/sys/arch/hpcmips/vr/
H A Dvrdmaau.c96 u_int32_t phy; in vrdmaau_set_aiuin() local
101 if ((err = vrdmaau_phy_addr(sc, addr, &phy))) in vrdmaau_set_aiuin()
104 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUIBAH_REG_W, phy >> 16); in vrdmaau_set_aiuin()
105 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUIBAL_REG_W, phy & 0xffff); in vrdmaau_set_aiuin()
113 u_int32_t phy; in vrdmaau_set_aiuout() local
118 if ((err = vrdmaau_phy_addr(sc, addr, &phy))) in vrdmaau_set_aiuout()
121 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUOBAH_REG_W, phy >> 16); in vrdmaau_set_aiuout()
122 bus_space_write_2(sc->sc_iot, sc->sc_ioh, AIUOBAL_REG_W, phy & 0xffff); in vrdmaau_set_aiuout()
130 u_int32_t phy; in vrdmaau_set_fir() local
135 if ((err = vrdmaau_phy_addr(sc, addr, &phy))) in vrdmaau_set_fir()
[all …]
/netbsd-src/sys/dev/fdt/
H A Dfdt_phy.c84 struct fdtbus_phy *phy = NULL; in fdtbus_phy_get_index() local
118 phy = kmem_alloc(sizeof(*phy), KM_SLEEP); in fdtbus_phy_get_index()
119 phy->phy_pc = pc; in fdtbus_phy_get_index()
120 phy->phy_priv = phy_priv; in fdtbus_phy_get_index()
133 return phy; in fdtbus_phy_get_index()
150 fdtbus_phy_put(struct fdtbus_phy *phy) in fdtbus_phy_put() argument
152 struct fdtbus_phy_controller *pc = phy->phy_pc; in fdtbus_phy_put()
154 pc->pc_funcs->release(pc->pc_dev, phy->phy_priv); in fdtbus_phy_put()
155 kmem_free(phy, sizeof(*phy)); in fdtbus_phy_put()
159 fdtbus_phy_device(struct fdtbus_phy *phy) in fdtbus_phy_device() argument
[all …]
/netbsd-src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/qca/
H A Dar9331.dtsi129 phy-mode = "mii";
130 phy-handle = <&phy_port4>;
144 phy-mode = "gmii";
182 phy-mode = "gmii";
193 phy-handle = <&phy_port0>;
194 phy-mode = "internal";
201 phy-handle = <&phy_port1>;
202 phy-mode = "internal";
209 phy-handle = <&phy_port2>;
210 phy-mode = "internal";
[all …]
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dls1021a-tsn.dts60 phy-handle = <&rgmii_phy6>;
61 phy-mode = "rgmii-id";
68 phy-handle = <&rgmii_phy3>;
69 phy-mode = "rgmii-id";
76 phy-handle = <&rgmii_phy4>;
77 phy-mode = "rgmii-id";
84 phy-handle = <&rgmii_phy5>;
85 phy-mode = "rgmii-id";
92 phy-mode = "rgmii";
106 phy-handle = <&sgmii_phy2>;
[all …]
H A Dorion5x-netgear-wnr854t.dts128 phy-handle = <&lan3phy>;
134 phy-handle = <&lan4phy>;
140 phy-handle = <&wanphy>;
152 phy-handle = <&lan1phy>;
158 phy-handle = <&lan2phy>;
166 lan3phy: ethernet-phy@0 {
168 compatible = "ethernet-phy-id0141.0cb0",
169 "ethernet-phy-ieee802.3-c22";
174 lan4phy: ethernet-phy@1 {
176 compatible = "ethernet-phy-id0141.0cb0",
[all …]
/netbsd-src/sys/arch/sandpoint/stand/altboot/
H A Dwm.c112 unsigned phy, bmsr, anlpar; member
161 DPRINTF(("PHY %d (%04x.%04x)\n", l->phy, in wm_init()
162 mii_read(l, l->phy, 2), mii_read(l, l->phy, 3))); in wm_init()
167 val = mii_read(l, l->phy, 0x11); in wm_init()
354 mii_read(struct local *l, int phy, int reg) in mii_read() argument
358 data = (2U << 26) | MPHY(phy) | MREG(reg); in mii_read()
367 mii_write(struct local *l, int phy, int reg, int val) in mii_write() argument
371 data = (1U << 26) | MPHY(phy) | MREG(reg) | (val & 0xffff); in mii_write()
405 int phy, ctl, sts, bound; in mii_initphy() local
407 for (phy = 0; phy < 32; phy++) { in mii_initphy()
[all …]
H A Dpcn.c123 unsigned phy, bmsr, anlpar; member
175 val = pcn_mii_read(l, l->phy, 24); in pcn_init()
297 pcn_mii_read(struct local *l, int phy, int reg) in pcn_mii_read() argument
299 pcn_bcr_write(l, PCN_BCR33, MREG(reg) | MPHY(phy)); in pcn_mii_read()
304 pcn_mii_write(struct local *l, int phy, int reg, int val) in pcn_mii_write() argument
306 pcn_bcr_write(l, PCN_BCR33, MREG(reg) | MPHY(phy)); in pcn_mii_write()
348 int phy, ctl, sts, bound; in mii_initphy() local
350 for (phy = 0; phy < 32; phy++) { in mii_initphy()
351 ctl = pcn_mii_read(l, phy, MII_BMCR); in mii_initphy()
352 sts = pcn_mii_read(l, phy, MII_BMSR); in mii_initphy()
[all …]
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-usb.dtsi17 usbphy0: usb-phy@0 {
18 compatible = "brcm,sr-usb-combo-phy";
20 #phy-cells = <1>;
29 phy-names = "phy0", "phy1";
39 phy-names = "phy0", "phy1";
44 usbphy1: usb-phy@10000 {
45 compatible = "brcm,sr-usb-combo-phy";
47 #phy-cells = <1>;
51 usbphy2: usb-phy@20000 {
52 compatible = "brcm,sr-usb-hs-phy";
[all …]

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