| /netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | radeon_rv730_dpm.c | 251 &table->ACPIState.levels[0].vddc); in rv730_populate_smc_acpi_state()
252 table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ? in rv730_populate_smc_acpi_state()
254 table->ACPIState.levels[0].gen2XSP = in rv730_populate_smc_acpi_state()
258 &table->ACPIState.levels[0].vddc); in rv730_populate_smc_acpi_state()
259 table->ACPIState.levels[0].gen2PCIE = 0; in rv730_populate_smc_acpi_state()
301 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in rv730_populate_smc_acpi_state()
302 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); in rv730_populate_smc_acpi_state()
303 table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); in rv730_populate_smc_acpi_state()
304 table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv730_populate_smc_acpi_state()
305 table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv730_populate_smc_acpi_state()
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| H A D | radeon_rv740_dpm.c | 339 &table->ACPIState.levels[0].vddc); in rv740_populate_smc_acpi_state()
340 table->ACPIState.levels[0].gen2PCIE = in rv740_populate_smc_acpi_state()
343 table->ACPIState.levels[0].gen2XSP = in rv740_populate_smc_acpi_state()
347 &table->ACPIState.levels[0].vddc); in rv740_populate_smc_acpi_state()
348 table->ACPIState.levels[0].gen2PCIE = 0; in rv740_populate_smc_acpi_state()
378 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv740_populate_smc_acpi_state()
379 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv740_populate_smc_acpi_state()
380 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv740_populate_smc_acpi_state()
381 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv740_populate_smc_acpi_state()
382 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv740_populate_smc_acpi_state()
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| H A D | radeon_cypress_dpm.c | 781 &smc_state->levels[0], in cypress_convert_power_state_to_smc()
788 &smc_state->levels[1], in cypress_convert_power_state_to_smc()
795 &smc_state->levels[2], in cypress_convert_power_state_to_smc()
800 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1; in cypress_convert_power_state_to_smc()
801 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2; in cypress_convert_power_state_to_smc()
802 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3; in cypress_convert_power_state_to_smc()
805 smc_state->levels[0].ACIndex = 2; in cypress_convert_power_state_to_smc()
806 smc_state->levels[1].ACIndex = 3; in cypress_convert_power_state_to_smc()
807 smc_state->levels[2].ACIndex = 4; in cypress_convert_power_state_to_smc()
809 smc_state->levels[0].ACIndex = 0; in cypress_convert_power_state_to_smc()
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| H A D | radeon_sumo_dpm.c | 352 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; in sumo_program_bsp()
416 m_a = asi * ps->levels[i].sclk / 100; in sumo_program_at()
675 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; in sumo_patch_boost_state()
767 sumo_program_power_level(rdev, &new_ps->levels[i], i); in sumo_program_power_levels_0_to_n()
849 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in sumo_set_uvd_clock_before_set_eng_clock()
850 current_ps->levels[current_ps->num_levels - 1].sclk) in sumo_set_uvd_clock_before_set_eng_clock()
867 if (new_ps->levels[new_ps->num_levels - 1].sclk < in sumo_set_uvd_clock_after_set_eng_clock()
868 current_ps->levels[current_ps->num_levels - 1].sclk) in sumo_set_uvd_clock_after_set_eng_clock()
1058 current_vddc = current_ps->levels[current_index].vddc_index; in sumo_patch_thermal_state()
1059 current_sclk = current_ps->levels[current_index].sclk; in sumo_patch_thermal_state()
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| H A D | radeon_rv770_dpm.c | 294 smc_state->levels[i].aT = cpu_to_be32(a_t); in rv770_populate_smc_t()
300 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].aT = in rv770_populate_smc_t()
314 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); in rv770_populate_smc_sp()
316 smc_state->levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1].bSP = in rv770_populate_smc_sp()
690 &smc_state->levels[0], in rv770_convert_power_state_to_smc()
697 &smc_state->levels[1], in rv770_convert_power_state_to_smc()
704 &smc_state->levels[2], in rv770_convert_power_state_to_smc()
709 smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1; in rv770_convert_power_state_to_smc()
710 smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2; in rv770_convert_power_state_to_smc()
711 smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3; in rv770_convert_power_state_to_smc()
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| H A D | radeon_trinity_dpm.c | 854 trinity_program_power_level(rdev, &new_ps->levels[i], i); in trinity_program_power_levels_0_to_n()
974 if (new_ps->levels[new_ps->num_levels - 1].sclk >= in trinity_set_uvd_clock_before_set_eng_clock()
975 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_before_set_eng_clock()
988 if (new_ps->levels[new_ps->num_levels - 1].sclk < in trinity_set_uvd_clock_after_set_eng_clock()
989 current_ps->levels[current_ps->num_levels - 1].sclk) in trinity_set_uvd_clock_after_set_eng_clock()
1336 ps->levels[0] = pi->boot_pl; in trinity_patch_boot_state()
1359 pi->current_ps.levels[0] = pi->boot_pl; in trinity_construct_boot_state()
1414 current_vddc = current_ps->levels[current_index].vddc_index; in trinity_patch_thermal_state()
1415 current_sclk = current_ps->levels[current_index].sclk; in trinity_patch_thermal_state()
1421 ps->levels[0].vddc_index = current_vddc; in trinity_patch_thermal_state()
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| H A D | radeon_ni_dpm.c | 1696 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = in ni_populate_smc_initial_state()
1698 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = in ni_populate_smc_initial_state()
1700 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = in ni_populate_smc_initial_state()
1702 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = in ni_populate_smc_initial_state()
1704 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = in ni_populate_smc_initial_state()
1706 table->initialState.levels[0].mclk.vDLL_CNTL = in ni_populate_smc_initial_state()
1708 table->initialState.levels[0].mclk.vMPLL_SS = in ni_populate_smc_initial_state()
1710 table->initialState.levels[0].mclk.vMPLL_SS2 = in ni_populate_smc_initial_state()
1712 table->initialState.levels[0].mclk.mclk_value = in ni_populate_smc_initial_state()
1715 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = in ni_populate_smc_initial_state()
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| H A D | radeon_si_dpm.c | 2322 smc_state->levels[0].dpm2.MaxPS = 0; in si_populate_power_containment_values()
2323 smc_state->levels[0].dpm2.NearTDPDec = 0; in si_populate_power_containment_values()
2324 smc_state->levels[0].dpm2.AboveSafeInc = 0; in si_populate_power_containment_values()
2325 smc_state->levels[0].dpm2.BelowSafeInc = 0; in si_populate_power_containment_values()
2326 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; in si_populate_power_containment_values()
2376 …smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / ma… in si_populate_power_containment_values()
2377 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; in si_populate_power_containment_values()
2378 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; in si_populate_power_containment_values()
2379 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; in si_populate_power_containment_values()
2380 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); in si_populate_power_containment_values()
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/ |
| H A D | align.h | 54 levels[0].log = log0;
55 levels[0].maxskip = maxskip0;
56 levels[1].log = log1;
57 levels[1].maxskip = maxskip1;
65 levels[i].normalize (); in normalize()
71 int log0 = MAX (f0.levels[0].log, f1.levels[0].log); in max()
72 int maxskip0 = MAX (f0.levels[0].maxskip, f1.levels[0].maxskip); in max()
73 int log1 = MAX (f0.levels[1].log, f1.levels[1].log); in max()
74 int maxskip1 = MAX (f0.levels[1].maxskip, f1.levels[1].maxskip); in max()
78 align_flags_tuple levels[2]; variable
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| /netbsd-src/external/gpl3/gcc/dist/gcc/ |
| H A D | align.h | 54 levels[0].log = log0;
55 levels[0].maxskip = maxskip0;
56 levels[1].log = log1;
57 levels[1].maxskip = maxskip1;
65 levels[i].normalize (); in normalize()
71 int log0 = MAX (f0.levels[0].log, f1.levels[0].log); in max()
72 int maxskip0 = MAX (f0.levels[0].maxskip, f1.levels[0].maxskip); in max()
73 int log1 = MAX (f0.levels[1].log, f1.levels[1].log); in max()
74 int maxskip1 = MAX (f0.levels[1].maxskip, f1.levels[1].maxskip); in max()
78 align_flags_tuple levels[2]; variable
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| /netbsd-src/tests/modules/x86_pte_tester/ |
| H A D | x86_pte_tester.c | 51 vaddr_t levels[NLEVEL]; member
89 pd_entry_t *pd = (pd_entry_t *)tester_ctx.levels[0]; in scan_l1()
92 pmap_kenter_pa(tester_ctx.levels[0], pa, VM_PROT_READ, 0); in scan_l1()
102 pmap_kremove(tester_ctx.levels[0], PAGE_SIZE); in scan_l1()
109 pd_entry_t *pd = (pd_entry_t *)tester_ctx.levels[1]; in scan_l2()
113 pmap_kenter_pa(tester_ctx.levels[1], pa, VM_PROT_READ, 0); in scan_l2()
129 pmap_kremove(tester_ctx.levels[1], PAGE_SIZE); in scan_l2()
136 pd_entry_t *pd = (pd_entry_t *)tester_ctx.levels[2]; in scan_l3()
140 pmap_kenter_pa(tester_ctx.levels[2], pa, VM_PROT_READ, 0); in scan_l3()
156 pmap_kremove(tester_ctx.levels[2], PAGE_SIZE); in scan_l3()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/ |
| H A D | clang-parse-diagnostics-file | 30 levels = {'error': False, 'fatal error': False, 'ignored': False,
33 levels['error'] = True
35 levels['fatal error'] = True
37 levels['ignored'] = True
39 levels['note'] = True
41 levels['warning'] = True
81 if levels[d.get('level')] or opts.all]
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| /netbsd-src/sys/arch/macppc/macppc/ |
| H A D | pic_heathrow.c | 157 uint32_t levels; in heathrow_reenable_irq() local
163 levels = in32rb(INT_STATE_REG_H); in heathrow_reenable_irq()
164 if (levels & mask) { in heathrow_reenable_irq()
171 levels = in32rb(INT_STATE_REG_L); in heathrow_reenable_irq()
172 if (levels & mask) { in heathrow_reenable_irq()
198 uint32_t irqs, events, levels; in heathrow_read_events() local
204 levels = in32rb(INT_LEVEL_REG_L) & heathrow->enable_mask_l; in heathrow_read_events()
205 events |= levels & heathrow->level_mask_l; in heathrow_read_events()
212 levels = in32rb(INT_LEVEL_REG_L) & heathrow->enable_mask_h; in heathrow_read_events()
213 events |= levels & heathrow->level_mask_h; in heathrow_read_events()
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| H A D | pic_ohare.c | 178 uint32_t levels; in ohare_reenable_irq() local
183 levels = in32rb(INT_STATE_REG); in ohare_reenable_irq()
184 if (levels & mask) { in ohare_reenable_irq()
204 uint32_t irqs, events, levels; in ohare_read_events() local
209 levels = in32rb(INT_LEVEL_REG) & ohare->enable_mask; in ohare_read_events()
210 events |= levels & ohare->level_mask; in ohare_read_events()
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| /netbsd-src/crypto/external/bsd/openssl.old/dist/crypto/x509v3/ |
| H A D | pcy_tree.c | 57 curr = tree->levels + tree->nlevel; in tree_print()
62 BIO_printf(err, "Printing Up to Level %ld\n", curr - tree->levels); in tree_print()
63 for (plev = tree->levels; plev != curr; plev++) { in tree_print()
67 (long)(plev - tree->levels), plev->flags); in tree_print()
178 if ((tree->levels = OPENSSL_zalloc(sizeof(*tree->levels)*(n+1))) == NULL) { in tree_init()
184 level = tree->levels; in tree_init()
426 if (curr == tree->levels) { in tree_prune()
473 curr = tree->levels + tree->nlevel - 1; in tree_calculate_authority_set()
484 curr = tree->levels; in tree_calculate_authority_set()
532 anyPolicy = tree->levels[tree->nlevel - 1].anyPolicy; in tree_calculate_user_set()
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| /netbsd-src/crypto/external/bsd/openssl/dist/crypto/x509/ |
| H A D | pcy_tree.c | 60 curr = tree->levels + tree->nlevel; in tree_print()
66 (long)(curr - tree->levels)); in tree_print()
67 for (plev = tree->levels; plev != curr; plev++) { in tree_print()
71 (long)(plev - tree->levels), plev->flags); in tree_print()
189 if ((tree->levels = OPENSSL_zalloc(sizeof(*tree->levels)*(n+1))) == NULL) { in tree_init()
195 level = tree->levels; in tree_init()
441 if (curr == tree->levels) { in tree_prune()
488 curr = tree->levels + tree->nlevel - 1; in tree_calculate_authority_set()
499 curr = tree->levels; in tree_calculate_authority_set()
547 anyPolicy = tree->levels[tree->nlevel - 1].anyPolicy; in tree_calculate_user_set()
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| /netbsd-src/crypto/external/bsd/openssl/dist/crypto/ |
| H A D | sparse_array.c | 52 int levels; member
88 if (l < sa->levels - 1) { in sa_doall()
166 for (level = sa->levels - 1; p != NULL && level > 0; level--) in ossl_sa_get()
192 for (;sa->levels < level; sa->levels++) { in ossl_sa_set()
203 for (level = sa->levels - 1; level > 0; level--) { in ossl_sa_set()
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| /netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| H A D | nuvoton-npcm750-evb.dts | 285 cooling-levels = <127 255>;
290 cooling-levels = /bits/ 8 <127 255>;
295 cooling-levels = /bits/ 8 <127 255>;
300 cooling-levels = /bits/ 8 <127 255>;
305 cooling-levels = /bits/ 8 <127 255>;
310 cooling-levels = /bits/ 8 <127 255>;
315 cooling-levels = /bits/ 8 <127 255>;
320 cooling-levels = /bits/ 8 <127 255>;
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_si_dpm.c | 2420 smc_state->levels[0].dpm2.MaxPS = 0; in si_populate_power_containment_values()
2421 smc_state->levels[0].dpm2.NearTDPDec = 0; in si_populate_power_containment_values()
2422 smc_state->levels[0].dpm2.AboveSafeInc = 0; in si_populate_power_containment_values()
2423 smc_state->levels[0].dpm2.BelowSafeInc = 0; in si_populate_power_containment_values()
2424 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; in si_populate_power_containment_values()
2473 …smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / ma… in si_populate_power_containment_values()
2474 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; in si_populate_power_containment_values()
2475 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; in si_populate_power_containment_values()
2476 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; in si_populate_power_containment_values()
2477 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); in si_populate_power_containment_values()
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| /netbsd-src/lib/libc/db/btree/ |
| H A D | bt_debug.c | 307 int levels; in __bt_stat() local
336 for (i = P_ROOT, levels = 0 ;; ++levels) { in __bt_stat()
339 if (levels == 0) in __bt_stat()
340 levels = 1; in __bt_stat()
351 levels, levels == 1 ? "" : "s", nkeys); in __bt_stat()
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| /netbsd-src/sys/arch/x86/x86/ |
| H A D | x86_softintr.c | 172 int levels = 0; in x86_intr_calculatemasks() local
179 levels |= 1 << q->ih_level; in x86_intr_calculatemasks()
180 intrlevel[irq] = levels; in x86_intr_calculatemasks()
181 if (levels) in x86_intr_calculatemasks()
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| /netbsd-src/sys/dev/fdt/ |
| H A D | pwm_fan.c | 80 const u_int *levels; in pwm_fan_attach() local
91 levels = fdtbus_get_prop(phandle, "cooling-levels", &len); in pwm_fan_attach()
99 sc->sc_levels[n] = be32toh(levels[n]); in pwm_fan_attach()
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| /netbsd-src/lib/libkvm/ |
| H A D | kvm_aarch64.c | 117 u_int levels = howmany(inputsz - page_shift, pte_shift); in _kvm_kvatop() local
122 u_int addr_shift = page_shift + (levels - 1) * pte_shift; in _kvm_kvatop()
155 if (--levels == 0) { in _kvm_kvatop()
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| /netbsd-src/tests/usr.bin/indent/ |
| H A D | t_misc.sh | 176 warning: Standard Input:5: Reached internal limit of 20 struct levels
177 warning: Standard Input:6: Reached internal limit of 20 struct levels
178 warning: Standard Input:6: Reached internal limit of 20 struct levels
179 warning: Standard Input:6: Reached internal limit of 20 struct levels
180 warning: Standard Input:6: Reached internal limit of 20 struct levels
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| /netbsd-src/external/gpl3/gcc.old/dist/fixincludes/ |
| H A D | fixinc.in | 209 levels=2
213 while [ -n "$dirs" ] && [ $levels -gt 0 ]
215 levels=`expr $levels - 1`
|