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Searched refs:isAvailable (Results 1 – 25 of 47) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
H A DDispatchStage.cpp51 const unsigned RegisterMask = PRF.isAvailable(RegDefs); in checkPRF()
64 if (RCU.isAvailable(NumMicroOps)) in checkRCU()
155 bool DispatchStage::isAvailable(const InstRef &IR) const { in isAvailable() function in llvm::mca::DispatchStage
H A DExecuteStage.cpp43 bool ExecuteStage::isAvailable(const InstRef &IR) const { in isAvailable() function in llvm::mca::ExecuteStage
44 if (Scheduler::Status S = HWS.isAvailable(IR)) { in isAvailable()
187 assert(isAvailable(IR) && "Scheduler is not available!"); in execute()
H A DEntryStage.cpp25 bool EntryStage::isAvailable(const InstRef & /* unused */) const { in isAvailable() function in llvm::mca::EntryStage
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/
H A DStage.h42 virtual bool isAvailable(const InstRef &IR) const { return true; } in isAvailable() function
63 return NextInSequence && NextInSequence->isAvailable(IR); in checkNextStage()
H A DEntryStage.h41 bool isAvailable(const InstRef &IR) const override;
H A DDispatchStage.h72 bool isAvailable(const InstRef &IR) const override;
H A DMicroOpQueueStage.h67 bool isAvailable(const InstRef &IR) const override { in isAvailable() function
H A DExecuteStage.h62 bool isAvailable(const InstRef &IR) const override;
H A DInOrderIssueStage.h88 bool isAvailable(const InstRef &) const override;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Support/
H A DCompression.cpp47 bool zlib::isAvailable() { return true; } in isAvailable() function in zlib
89 bool zlib::isAvailable() { return false; } in isAvailable() function in zlib
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
H A DRegisterFile.h70 bool isAvailable() const { return hasKnownWriteBackCycle(); } in isAvailable() function
279 unsigned isAvailable(ArrayRef<MCPhysReg> Regs) const;
H A DLSUnit.h256 virtual Status isAvailable(const InstRef &IR) const = 0;
457 Status isAvailable(const InstRef &IR) const override;
H A DRetireControlUnit.h84 bool isAvailable(unsigned Quantity = 1) const {
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DLatencyPriorityQueue.cpp103 if (SU->isAvailable) return; // All preds scheduled. in AdjustPriorityOfUnscheduledPreds()
106 if (!OnlyAvailablePred || !OnlyAvailablePred->isAvailable) return; in AdjustPriorityOfUnscheduledPreds()
H A DPostRASchedulerList.cpp536 if (!SUnits[i].NumPredsLeft && !SUnits[i].isAvailable) { in ListScheduleTopDown()
538 SUnits[i].isAvailable = true; in ListScheduleTopDown()
557 PendingQueue[i]->isAvailable = true; in ListScheduleTopDown()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGVLIW.cpp176 SUnits[i].isAvailable = true; in listScheduleTopDown()
190 PendingQueue[i]->isAvailable = true; in listScheduleTopDown()
H A DScheduleDAGFast.cpp155 PredSU->isAvailable = true; in ReleasePred()
342 NewSU->isAvailable = true; in CopyAndMoveSuccessors()
534 RootSU->isAvailable = true; in ListScheduleBottomUp()
605 TrySU->isAvailable = false; in ListScheduleBottomUp()
618 if (NotReady[i]->isAvailable) in ListScheduleBottomUp()
H A DScheduleDAGRRList.cpp420 PredSU->isAvailable = true; in ReleasePred()
616 if (PendingQueue[i]->isAvailable) { in ReleasePending()
822 if (PredSU->isAvailable) { in CapturePred()
823 PredSU->isAvailable = false; in CapturePred()
913 SU->isAvailable = true; in UnscheduleNodeBottomUp()
1127 NewSU->isAvailable = true; in TryUnfoldSU()
1448 if (SU->isAvailable && !SU->NodeQueueId) { in releaseInterferences()
1519 if (BtSU->isAvailable) { in PickNodeToScheduleBottomUp()
1520 BtSU->isAvailable = false; in PickNodeToScheduleBottomUp()
1530 if (!TrySU->isAvailable || !TrySU->NodeQueueId) { in PickNodeToScheduleBottomUp()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h283 bool isAvailable : 1; ///< True once available. variable
312 isPending(false), isAvailable(false), isScheduled(false), in SUnit()
323 isPending(false), isAvailable(false), isScheduled(false), in SUnit()
332 hasPhysRegClobbers(false), isPending(false), isAvailable(false), in SUnit()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/WindowsManifest/
H A DWindowsManifestMerger.h36 bool isAvailable();
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DCompression.h30 bool isAvailable();
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp40 Scheduler::Status Scheduler::isAvailable(const InstRef &IR) { in isAvailable() function in llvm::mca::Scheduler
55 LSUnit::Status LSS = LSU.isAvailable(IR); in isAvailable()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/
H A DPipeline.cpp62 while (!Err && FirstStage.isAvailable(IR)) in runCycle()
/netbsd-src/external/apache2/llvm/dist/clang/include/clang/Lex/
H A DModuleMap.h176 bool isAvailable() const { in isAvailable() function
177 return getModule()->isAvailable(); in isAvailable()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Object/
H A DDecompressor.cpp22 if (!zlib::isAvailable()) in create()

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