Searched refs:hasVGPRs (Results 1 – 4 of 4) sorted by relevance
155 return !hasVGPRs(RC) && !hasAGPRs(RC); in isSGPRClass()167 return hasAGPRs(RC) && !hasVGPRs(RC); in isAGPRClass()171 bool hasVGPRs(const TargetRegisterClass *RC) const;178 return hasVGPRs(RC) || hasAGPRs(RC); in hasVectorRegisters()
2079 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const { in hasVGPRs() function in SIRegisterInfo2246 return RC && hasVGPRs(RC); in isVGPR()2457 if (hasVGPRs(&RC)) in isProperlyAlignedRC()
892 Opcode = (RI.hasVGPRs(SrcRC)) ? in copyPhysReg()894 } else if (RI.hasVGPRs(RC) && RI.hasAGPRs(SrcRC)) { in copyPhysReg()896 } else if ((Size % 64 == 0) && RI.hasVGPRs(RC) && in copyPhysReg()1806 if (RI.hasVGPRs(EltRC)) { in expandPostRAPseudo()2509 return RI.hasVGPRs(RC) && NumInsts <= 6; in canInsertSelect()3807 const bool IsVGPR = RI.hasVGPRs(RC); in verifyInstruction()3854 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) { in verifyInstruction()5453 if (RI.hasVGPRs(DstRC)) { in legalizeOperands()6875 if (RI.hasVGPRs(NewDstRC) || NewDstRC == &AMDGPU::VReg_1RegClass) in getDestEquivalentVGPRClass()
1173 !TRI->hasVGPRs(TRI->getRegClass(Desc.OpInfo[I].RegClass))) in legalizeScalarOperands()