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Searched refs:getTII (Results 1 – 10 of 10) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonRDFOpt.cpp220 auto &HII = static_cast<const HexagonInstrInfo&>(DFG.getTII()); in rewrite()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp546 Builder.getTII().get(Preferred.ExtendOpcode == TargetOpcode::G_SEXT in applyCombineExtendingLoads()
1916 MI.setDesc(MIB.getTII().get(TargetOpcode::G_SHL)); in applyCombineMulToShl()
2684 return Builder.getTII().produceSameValue(*I1, *I2, &MRI); in matchEqualDefs()
3212 Def->setDesc(Builder.getTII().get(TargetOpcode::G_OR)); in applyNotCmp()
3215 Def->setDesc(Builder.getTII().get(TargetOpcode::G_AND)); in applyNotCmp()
3265 MI.setDesc(Builder.getTII().get(TargetOpcode::G_AND)); in applyXorOfAndWithSameReg()
3687 if (Builder.getTII().isExtendLikelyToBeFolded(*ExtMI, MRI)) in matchExtendThroughPhis()
3899 MI.setDesc(Builder.getTII().get(IsFSHL ? TargetOpcode::G_ROTL in applyFunnelShiftToRotate()
H A DMachineIRBuilder.cpp41 MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode)); in buildInstrNoInsert()
60 getTII().get(TargetOpcode::DBG_VALUE), in buildDirectDbgValue()
73 getTII().get(TargetOpcode::DBG_VALUE), in buildIndirectDbgValue()
H A DLegalizerHelper.cpp608 << MIRBuilder.getTII().getName(Opc) << "\n"); in createMemLibcall()
617 isLibCallInTailPosition(MIRBuilder.getTII(), MI); in createMemLibcall()
2383 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); in widenScalar()
2916 MI.setDesc(MIRBuilder.getTII().get(NewOpcode)); in changeOpcode()
2962 const auto &TII = MIRBuilder.getTII(); in lower()
5229 const auto &TII = MIRBuilder.getTII(); in lowerBitCount()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsLegalizerInfo.cpp469 .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(), in SelectMSA3OpIntrinsic()
H A DMipsCallLowering.cpp606 MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in lowerCall()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DRDFGraph.h662 const TargetInstrInfo &getTII() const { return TII; } in getTII() function
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h264 const TargetInstrInfo &getTII() { in getTII() function
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp1812 MI.setDesc(B.getTII().get(TargetOpcode::G_BITCAST)); in legalizeAddrSpaceCast()
2728 Register LiveIn = getFunctionLiveInPhysReg(B.getMF(), B.getTII(), SrcReg, *ArgRC, in loadInputValue()
4163 MI.setDesc(B.getTII().get(NewOpcode)); in legalizeImageIntrinsic()
4502 MI.setDesc(B.getTII().get(AMDGPU::G_AMDGPU_S_BUFFER_LOAD)); in legalizeSBufferLoad()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DRDFGraph.cpp227 OS << Print<NodeId>(P.Obj.Id, P.G) << ": " << P.G.getTII().getName(Opc); in operator <<()