Searched refs:getSubRegClass (Results 1 – 6 of 6) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 196 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
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| H A D | SIInstrInfo.cpp | 3811 RI.getSubRegClass(RC, MO.getSubReg()); in verifyInstruction()
6340 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
6347 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
6404 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitAddSub()
6405 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitAddSub()
6470 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
6475 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
6488 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
6577 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0); in splitScalar64BitBCNT()
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| H A D | SIFixSGPRCopies.cpp | 272 SrcRC = TRI->getSubRegClass(SrcRC, SrcSubReg); in foldVGPRCopyIntoRegSequence()
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| H A D | SIWholeQuadMode.cpp | 1434 regClass = TRI->getSubRegClass(regClass, SubReg); in lowerCopyInstrs()
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| H A D | SIRegisterInfo.cpp | 2131 const TargetRegisterClass *SIRegisterInfo::getSubRegClass( in getSubRegClass() function in SIRegisterInfo
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| H A D | SIISelLowering.cpp | 3973 TRI->getSubRegClass(Src0RC, AMDGPU::sub0); in EmitInstrWithCustomInserter()
3975 TRI->getSubRegClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
4058 TRI->getSubRegClass(Src2RC, AMDGPU::sub0); in EmitInstrWithCustomInserter()
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