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Searched refs:getRegState (Results 1 – 10 of 10) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZPostRewrite.cpp124 .addReg(MBBI->getOperand(1).getReg(), getRegState(MBBI->getOperand(1))); in selectSELRMux()
131 .addReg(MBBI->getOperand(2).getReg(), getRegState(MBBI->getOperand(2))); in selectSELRMux()
201 .addReg(MI.getOperand(2).getReg(), getRegState(MI.getOperand(2))); in expandCondMove()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp638 unsigned RSA = getRegState(AdrOp); in splitMemRef()
742 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
750 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg()); in splitCombine()
765 unsigned RS = getRegState(Op1); in splitExt()
799 unsigned RS = getRegState(Op1); in splitShift()
919 unsigned RS1 = getRegState(Op1); in splitAslOr()
920 unsigned RS2 = getRegState(Op2); in splitAslOr()
H A DHexagonExpandCondsets.cpp640 unsigned PredState = getRegState(PredOp) & ~RegState::Kill; in genCondTfrFor()
644 unsigned SrcState = getRegState(SrcOp); in genCondTfrFor()
697 unsigned S = getRegState(ST); in split()
886 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt()
H A DHexagonInstrInfo.cpp1093 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1110 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1115 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1131 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1133 .addReg(SrcOp.getReg(), getRegState(SrcOp)) in expandPostRAPseudo()
1148 .addReg(BaseOp.getReg(), getRegState(BaseOp) & ~RegState::Kill) in expandPostRAPseudo()
1153 .addReg(BaseOp.getReg(), getRegState(BaseOp)) in expandPostRAPseudo()
1286 unsigned PState = getRegState(Op1); in expandPostRAPseudo()
1319 unsigned PState = getRegState(Op1); in expandPostRAPseudo()
H A DHexagonConstPropagation.cpp3005 .addReg(R1.Reg, getRegState(Acc), R1.SubReg); in rewriteHexConstUses()
3035 .addReg(Src1.getReg(), getRegState(Src1), Src1.getSubReg()) in rewriteHexConstUses()
3036 .addReg(OpR2.getReg(), getRegState(OpR2), OpR2.getSubReg()) in rewriteHexConstUses()
3071 .addReg(SR.Reg, getRegState(SO), SR.SubReg); in rewriteHexConstUses()
3103 .addReg(SR.Reg, getRegState(SO), SR.SubReg); in rewriteHexConstUses()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DUnreachableBlockElim.cpp194 .addReg(InputReg, getRegState(Input), InputSub); in runOnMachineFunction()
H A DMachinePipeliner.cpp406 .addReg(RegOp.getReg(), getRegState(RegOp), in preprocessPhiNodes()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h528 inline unsigned getRegState(const MachineOperand &RegOp) { in getRegState() function
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMConstantIslandPass.cpp1990 getRegState(Cmp.MI->getOperand(0))) in optimizeThumb2Branches()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp4764 unsigned MaskState = getRegState(MIB->getOperand(1)); in expandPostRAPseudo()