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Searched refs:getReg (Results 1 – 25 of 579) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp251 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
274 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
312 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
316 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
317 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
321 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
322 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
327 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
331 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
332 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
63 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
64 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
65 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
110 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) in lowerSubvectorLoad()
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H A DSystemZShortenInst.cpp78 Register Reg = MI.getOperand(0).getReg(); in shortenIIF()
110 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) { in shortenOn0()
120 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && in shortenOn01()
121 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) { in shortenOn01()
132 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && in shortenOn001()
133 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() && in shortenOn001()
134 SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) { in shortenOn001()
158 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 && in shortenFPConv()
159 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) { in shortenFPConv()
184 if (SystemZMC::getFirstReg(DstMO.getReg()) < 16 && in shortenFusedFPOp()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineCopyPropagation.cpp123 RegsToInvalidate.insert(MI->getOperand(0).getReg().asMCReg()); in invalidateRegister()
124 RegsToInvalidate.insert(MI->getOperand(1).getReg().asMCReg()); in invalidateRegister()
146 markRegsUnavailable({MI->getOperand(0).getReg().asMCReg()}, TRI); in clobberRegister()
157 MCRegister Def = MI->getOperand(0).getReg().asMCReg(); in trackCopy()
158 MCRegister Src = MI->getOperand(1).getReg().asMCReg(); in trackCopy()
205 !TRI.isSubRegisterEq(AvailCopy->getOperand(1).getReg(), Reg)) in findAvailBackwardCopy()
208 Register AvailSrc = AvailCopy->getOperand(1).getReg(); in findAvailBackwardCopy()
209 Register AvailDef = AvailCopy->getOperand(0).getReg(); in findAvailBackwardCopy()
229 !TRI.isSubRegisterEq(AvailCopy->getOperand(0).getReg(), Reg)) in findAvailCopy()
234 Register AvailSrc = AvailCopy->getOperand(1).getReg(); in findAvailCopy()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp38 return computeKnownAlignment(MI->getOperand(1).getReg(), Depth); in computeKnownAlignment()
53 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
171 computeKnownBitsImpl(MI.getOperand(i + 1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
206 Register SrcReg = Src.getReg(); in computeKnownBitsImpl()
245 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
247 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
254 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
256 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
266 LLT Ty = MRI.getType(MI.getOperand(1).getReg()); in computeKnownBitsImpl()
272 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
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H A DCombinerHelper.cpp154 Register DstReg = MI.getOperand(0).getReg(); in matchCombineCopy()
155 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineCopy()
159 Register DstReg = MI.getOperand(0).getReg(); in applyCombineCopy()
160 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineCopy()
186 Register Reg = MO.getReg(); in matchCombineConcatVectors()
195 Ops.push_back(BuildVecMO.getReg()); in matchCombineConcatVectors()
204 assert(MRI.getType(Undef->getOperand(0).getReg()) == in matchCombineConcatVectors()
211 Ops.push_back(Undef->getOperand(0).getReg()); in matchCombineConcatVectors()
224 Register DstReg = MI.getOperand(0).getReg(); in applyCombineConcatVectors()
255 LLT DstType = MRI.getType(MI.getOperand(0).getReg()); in matchCombineShuffleVector()
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H A DLegalizerHelper.cpp253 Regs[StartIdx + I] = MI.getOperand(I).getReg(); in getUnmergeResults()
293 PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0); in buildLCMMergePieces()
295 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in buildLCMMergePieces()
302 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0); in buildLCMMergePieces()
340 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); in buildLCMMergePieces()
342 AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); in buildLCMMergePieces()
358 Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0); in buildLCMMergePieces()
558 Args.push_back({MI.getOperand(i).getReg(), OpType}); in simpleLibcall()
559 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType}, in simpleLibcall()
571 Register Reg = MI.getOperand(i).getReg(); in createMemLibcall()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp122 Register DstReg = MI.getOperand(0).getReg(); in applyBank()
123 Register SrcReg = MI.getOperand(1).getReg(); in applyBank()
137 MRI.setRegBank(True.getReg(0), *NewBank); in applyBank()
138 MRI.setRegBank(False.getReg(0), *NewBank); in applyBank()
149 Register DstReg = MI.getOperand(0).getReg(); in applyBank()
160 Register Reg = Op.getReg(); in applyBank()
309 Register Reg = MI.getOperand(RegSrcOpIdx[I]).getReg(); in addMappingFromTable()
314 unsigned SizeI = getSizeInBits(MI.getOperand(I).getReg(), MRI, *TRI); in addMappingFromTable()
469 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
495 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI); in getInstrAlternativeMappings()
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H A DAMDGPULegalizerInfo.cpp1763 return B.buildShl(S32, GetReg, ShiftAmt).getReg(0); in getSegmentAperture()
1787 return B.buildLoad(S32, LoadAddr, *MMO).getReg(0); in getSegmentAperture()
1796 Register Dst = MI.getOperand(0).getReg(); in legalizeAddrSpaceCast()
1797 Register Src = MI.getOperand(1).getReg(); in legalizeAddrSpaceCast()
1849 B.buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), Src, FlatNull.getReg(0)); in legalizeAddrSpaceCast()
1850 B.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0)); in legalizeAddrSpaceCast()
1872 B.buildICmp(CmpInst::ICMP_NE, LLT::scalar(1), Src, SegmentNull.getReg(0)); in legalizeAddrSpaceCast()
1875 Register SrcAsInt = B.buildPtrToInt(S32, Src).getReg(0); in legalizeAddrSpaceCast()
1889 Register Src = MI.getOperand(1).getReg(); in legalizeFrint()
1907 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2); in legalizeFrint()
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H A DSIShrinkInstructions.cpp71 Register Reg = Src0.getReg(); in foldImmediates()
248 unsigned Vgpr = TRI.getHWRegIndex(Op.getReg()); in shrinkMIMG()
359 if (Dest->getReg().isVirtual() && SrcReg->isReg()) { in shrinkScalarLogicOp()
360 MRI.setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg()); in shrinkScalarLogicOp()
361 MRI.setRegAllocationHint(SrcReg->getReg(), 0, Dest->getReg()); in shrinkScalarLogicOp()
365 if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) { in shrinkScalarLogicOp()
373 MI.getOperand(2).ChangeToRegister(Dest->getReg(), /*IsDef*/ false, in shrinkScalarLogicOp()
395 if (Reg.isPhysical() && MO.getReg().isPhysical()) { in instAccessReg()
396 if (TRI.regsOverlap(Reg, MO.getReg())) in instAccessReg()
398 } else if (MO.getReg() == Reg && Reg.isVirtual()) { in instAccessReg()
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H A DSIFixSGPRCopies.cpp131 if (!MI.getOperand(i).isReg() || !MI.getOperand(i).getReg().isVirtual()) in hasVectorOperands()
134 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVectorOperands()
144 Register DstReg = Copy.getOperand(0).getReg(); in getCopyRegClasses()
145 Register SrcReg = Copy.getOperand(1).getReg(); in getCopyRegClasses()
180 Register DstReg = MI.getOperand(0).getReg(); in tryChangeVGPRtoSGPRinCopy()
181 Register SrcReg = Src.getReg(); in tryChangeVGPRtoSGPRinCopy()
222 Register DstReg = MI.getOperand(0).getReg(); in foldVGPRCopyIntoRegSequence()
234 if (CopyUse.getOperand(0).getReg().isPhysical()) in foldVGPRCopyIntoRegSequence()
261 MI.getOperand(0).setReg(CopyUse.getOperand(0).getReg()); in foldVGPRCopyIntoRegSequence()
265 Register SrcReg = MI.getOperand(I).getReg(); in foldVGPRCopyIntoRegSequence()
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H A DSIFoldOperands.cpp271 bool HaveNonDbgCarryUse = !MRI.use_nodbg_empty(Dst1.getReg()); in updateOperand()
273 const TargetRegisterClass *Dst0RC = MRI.getRegClass(Dst0.getReg()); in updateOperand()
279 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), Dst1.getReg()) in updateOperand()
318 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI); in updateOperand()
425 !TII->getRegisterInfo().isVGPR(MRI, OtherOp.getReg())) in tryAddToFoldList()
508 for (MachineInstr *SubDef = MRI.getVRegDef(Sub->getReg()); in getRegSeqInit()
509 SubDef && Sub->isReg() && Sub->getReg().isVirtual() && in getRegSeqInit()
511 SubDef = MRI.getVRegDef(Sub->getReg())) { in getRegSeqInit()
518 if (!Op->isReg() || Op->getReg().isPhysical()) in getRegSeqInit()
555 Register UseReg = OpToFold.getReg(); in tryToFoldACImm()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostLegalizerLowering.cpp222 Register Dst = MI.getOperand(0).getReg(); in matchREV()
223 Register Src = MI.getOperand(1).getReg(); in matchREV()
252 Register Dst = MI.getOperand(0).getReg(); in matchTRN()
257 Register V1 = MI.getOperand(1).getReg(); in matchTRN()
258 Register V2 = MI.getOperand(2).getReg(); in matchTRN()
273 Register Dst = MI.getOperand(0).getReg(); in matchUZP()
278 Register V1 = MI.getOperand(1).getReg(); in matchUZP()
279 Register V2 = MI.getOperand(2).getReg(); in matchUZP()
289 Register Dst = MI.getOperand(0).getReg(); in matchZip()
294 Register V1 = MI.getOperand(1).getReg(); in matchZip()
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H A DAArch64InstructionSelector.cpp603 getConstantVRegValWithLookThrough(Root.getReg(), MRI, true); in getImmedFromMO()
622 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in unsupportedBinOp()
640 if (!Register::isVirtualRegister(MO.getReg())) { in unsupportedBinOp()
645 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
775 const Register DstReg = I.getOperand(0).getReg(); in isValidCopy()
776 const Register SrcReg = I.getOperand(1).getReg(); in isValidCopy()
815 RegOp.setReg(SubRegCopy.getReg(0)); in copySubReg()
819 if (!Register::isPhysicalRegister(I.getOperand(0).getReg())) in copySubReg()
820 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI); in copySubReg()
833 Register DstReg = I.getOperand(0).getReg(); in getRegClassesForCopy()
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H A DAArch64RegisterBankInfo.cpp293 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
314 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
350 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI); in getInstrAlternativeMappings()
442 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getSameKindOfOperandsMapping()
458 LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg()); in getSameKindOfOperandsMapping()
504 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
519 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1); in hasFPConstraints()
596 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
597 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
607 LLT ShiftAmtTy = MRI.getType(MI.getOperand(2).getReg()); in getInstrMapping()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp110 printRegName(O, Dst.getReg()); in printInst()
112 printRegName(O, MO1.getReg()); in printInst()
115 printRegName(O, MO2.getReg()); in printInst()
132 printRegName(O, Dst.getReg()); in printInst()
134 printRegName(O, MO1.getReg()); in printInst()
150 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
164 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
169 printRegName(O, MI->getOperand(1).getReg()); in printInst()
179 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
193 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp160 Register Reg = Op->getReg(); in getVRegDefOrNull()
287 Register RegOp = VisitedPHI->getOperand(PHIOp).getReg(); in collectUnprimedAccPHIs()
295 Register Reg = Instr->getOperand(1).getReg(); in collectUnprimedAccPHIs()
334 Register RegOp = PHI->getOperand(PHIOp).getReg(); in convertUnprimedAccPHIs()
341 assert(MRI->getRegClass(PHIInput->getOperand(1).getReg()) == in convertUnprimedAccPHIs()
359 PrimedAccPHI->getOperand(0).getReg(), false), in convertUnprimedAccPHIs()
434 Register Src = MI.getOperand(1).getReg(); in simplifyCode()
435 Register Dst = MI.getOperand(0).getReg(); in simplifyCode()
472 unsigned MIDestReg = MI.getOperand(0).getReg(); in simplifyCode()
511 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); in simplifyCode()
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H A DPPCVSXCopy.cpp94 if ( IsVSReg(DstMO.getReg(), MRI) && in processBlock()
95 !IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
100 assert((IsF8Reg(SrcMO.getReg(), MRI) || in processBlock()
101 IsVSSReg(SrcMO.getReg(), MRI) || in processBlock()
102 IsVSFReg(SrcMO.getReg(), MRI)) && in processBlock()
115 } else if (!IsVSReg(DstMO.getReg(), MRI) && in processBlock()
116 IsVSReg(SrcMO.getReg(), MRI)) { in processBlock()
121 assert((IsF8Reg(DstMO.getReg(), MRI) || in processBlock()
122 IsVSFReg(DstMO.getReg(), MRI) || in processBlock()
123 IsVSSReg(DstMO.getReg(), MRI)) && in processBlock()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMRegisterBankInfo.cpp239 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
274 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
284 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
297 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
304 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
318 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
319 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
327 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
328 LLT FromTy = MRI.getType(MI.getOperand(1).getReg()); in getInstrMapping()
337 LLT ToTy = MRI.getType(MI.getOperand(0).getReg()); in getInstrMapping()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h57 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt()
58 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineAnyExt()
106 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt()
107 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineZExt()
165 Register DstReg = MI.getOperand(0).getReg(); in tryCombineSExt()
166 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineSExt()
222 Register DstReg = MI.getOperand(0).getReg(); in tryCombineTrunc()
223 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg()); in tryCombineTrunc()
242 const Register MergeSrcReg = SrcMI->getOperand(1).getReg(); in tryCombineTrunc()
286 SrcRegs[i] = SrcMI->getOperand(i + 1).getReg(); in tryCombineTrunc()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp213 Register R = Op.getReg(); in isFixedInstr()
261 Register T = MO.getReg(); in partitionRegisters()
374 Register Rs = MI->getOperand(1).getReg(); in profit()
375 Register Rt = MI->getOperand(2).getReg(); in profit()
442 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
501 Register PR = Cond[1].getReg(); in collectIndRegsForLoop()
509 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg()); in collectIndRegsForLoop()
537 Register R = MD.getReg(); in collectIndRegsForLoop()
553 Register T = UseI->getOperand(0).getReg(); in collectIndRegsForLoop()
602 Register R = Op.getReg(); in createHalfInstr()
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H A DHexagonInstrInfo.cpp202 Register Reg = MO.getReg(); in parseOperands()
207 Uses.push_back(MO.getReg()); in parseOperands()
210 Defs.push_back(MO.getReg()); in parseOperands()
267 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
281 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
315 return MI.getOperand(2).getReg(); in isStoreToStackSlot()
333 return MI.getOperand(3).getReg(); in isStoreToStackSlot()
641 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1). in insertBranch()
642 addReg(Cond[2].getReg(), Flags2).addMBB(TBB); in insertBranch()
644 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1). in insertBranch()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp580 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { in getReg() function
638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
640 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
710 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
712 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
717 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp108 assert(MO.isReg() && MO.getReg()); in transferImpOps()
122 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
166 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
191 Register StatusReg = MI.getOperand(1).getReg(); in expandCMP_SWAP()
196 Register AddrReg = MI.getOperand(2).getReg(); in expandCMP_SWAP()
197 Register DesiredReg = MI.getOperand(3).getReg(); in expandCMP_SWAP()
198 Register NewReg = MI.getOperand(4).getReg(); in expandCMP_SWAP()
217 BuildMI(LoadCmpBB, DL, TII->get(LdarOp), Dest.getReg()) in expandCMP_SWAP()
220 .addReg(Dest.getReg(), getKillRegState(Dest.isDead())) in expandCMP_SWAP()
271 Register StatusReg = MI.getOperand(2).getReg(); in expandCMP_SWAP_128()
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12345678910>>...24