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Searched refs:getKillRegState (Results 1 – 25 of 67) sorted by relevance

123

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp156 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandArith()
157 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
161 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandArith()
162 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandArith()
189 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLogic()
190 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic()
197 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLogic()
198 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandLogic()
237 .addReg(DstLoReg, getKillRegState(SrcIsKill)) in expandLogicImm()
247 .addReg(DstHiReg, getKillRegState(SrcIsKill)) in expandLogicImm()
[all …]
H A DAVRInstrInfo.cpp53 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
62 .addReg(SrcLo, getKillRegState(KillSrc)); in copyPhysReg()
64 .addReg(SrcHi, getKillRegState(KillSrc)); in copyPhysReg()
78 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
155 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
H A DAVRRelaxMemOperations.cpp112 .addReg(Src.getReg(), getKillRegState(Src.isKill())); in relax()
116 .addDef(Ptr.getReg(), getKillRegState(Ptr.isKill())); in relax()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp323 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
331 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
335 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
346 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
363 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
367 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
411 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
414 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
417 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
420 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp53 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
63 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
71 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
98 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
H A DMLxExpansionPass.cpp291 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
292 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction()
302 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
303 .addReg(AccReg, getKillRegState(AccKill)); in ExpandFPMLxInstruction()
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
H A DARMLoadStoreOptimizer.cpp744 .addReg(Base, getKillRegState(KillOldBase)); in CreateLoadStoreMulti()
747 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
757 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
763 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
768 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
810 .addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
819 MIB.addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
825 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti()
849 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second)) in CreateLoadStoreDouble()
850 .addReg(Regs[1].first, getKillRegState(Regs[1].second)); in CreateLoadStoreDouble()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp37 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
40 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
135 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
140 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEISelLowering.cpp1822 .addReg(Tmp1, getKillRegState(true)) in prepareMBB()
1826 .addReg(Tmp2, getKillRegState(true)) in prepareMBB()
1838 .addReg(Tmp1, getKillRegState(true)) in prepareMBB()
1841 .addReg(Tmp2, getKillRegState(true)) in prepareMBB()
1883 .addReg(Tmp1, getKillRegState(true)) in prepareSymbol()
1887 .addReg(Tmp2, getKillRegState(true)) in prepareSymbol()
1903 .addReg(Tmp1, getKillRegState(true)) in prepareSymbol()
1907 .addReg(Tmp2, getKillRegState(true)) in prepareSymbol()
1910 .addReg(Tmp3, getKillRegState(true)) in prepareSymbol()
1926 .addReg(Tmp1, getKillRegState(true)) in prepareSymbol()
[all …]
H A DVEInstrInfo.cpp366 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
384 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
385 .addReg(SubTmp, getKillRegState(true)); in copyPhysReg()
390 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
476 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
483 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
490 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
497 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
899 .addReg(Src, getKillRegState(KillSrc)); in expandPostRAPseudo()
913 .addReg(Src, getKillRegState(KillSrc)) in expandPostRAPseudo()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrBuilder.h159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
147 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
190 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
H A DXCoreInstrInfo.cpp340 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
352 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
375 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp725 .addReg(VReg1, getKillRegState(true)) in generateLoadForNewConst()
927 .addReg(RegX, getKillRegState(KillX)) in reassociateFMA()
928 .addReg(RegM21, getKillRegState(KillM21)) in reassociateFMA()
929 .addReg(RegM22, getKillRegState(KillM22)); in reassociateFMA()
932 .addReg(RegY, getKillRegState(KillY)) in reassociateFMA()
933 .addReg(RegM31, getKillRegState(KillM31)) in reassociateFMA()
934 .addReg(RegM32, getKillRegState(KillM32)); in reassociateFMA()
944 .addReg(NewVRB, getKillRegState(true)) in reassociateFMA()
945 .addReg(NewVRA, getKillRegState(true)); in reassociateFMA()
964 .addReg(RegM11, getKillRegState(KillM11)) in reassociateFMA()
[all …]
H A DPPCFrameLowering.cpp811 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
845 .addReg(ScratchReg, getKillRegState(!HasROPProtect)) in emitPrologue()
863 .addReg(ScratchReg, getKillRegState(true)) in emitPrologue()
873 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
978 .addReg(TOCReg, getKillRegState(true)) in emitPrologue()
1776 .addReg(TempReg, getKillRegState(i == e-1)); in emitEpilogue()
1852 .addReg(TempReg, getKillRegState(i == e-1)); in emitEpilogue()
2432 getKillRegState(true)), in spillCalleeSavedRegisters()
2448 .addReg(VSRContainingGPRs[Dst].first, getKillRegState(true)) in spillCalleeSavedRegisters()
2449 .addReg(VSRContainingGPRs[Dst].second, getKillRegState(true)); in spillCalleeSavedRegisters()
[all …]
H A DPPCRegisterInfo.cpp591 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); in lowerDynamicAlloc()
599 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); in lowerDynamicAlloc()
679 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in prepareDynamicAlloca()
696 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in prepareDynamicAlloca()
796 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); in lowerCRSpilling()
956 RegState::Implicit | getKillRegState(MI.getOperand(0).isKill())); in lowerCRBitSpilling()
1089 .addReg(Reg, getKillRegState(IsKilled)), in lowerACCSpilling()
1092 .addReg(Reg + 1, getKillRegState(IsKilled)), in lowerACCSpilling()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp54 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
58 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
103 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp278 .addReg(Src, getKillRegState(IsKill)); in insertCopy()
363 .addReg(Src0, getKillRegState(KillSrc0), SubReg0) in transformInstruction()
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1); in transformInstruction()
H A DAArch64InstrInfo.cpp3197 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI); in copyPhysRegTuple()
3221 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI); in copyGPRRegTuple()
3250 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
3253 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
3275 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
3280 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
3293 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
3303 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
3341 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
3352 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
[all …]
H A DAArch64SIMDInstrOpt.cpp434 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement()
436 unsigned Src1IsKill = getKillRegState(MI.getOperand(2).isKill()); in optimizeVectElement()
442 unsigned Src2IsKill = getKillRegState(MI.getOperand(3).isKill()); in optimizeVectElement()
642 StRegKill[i] = getKillRegState(DefiningMI->getOperand(2*i+1).isKill()); in processSeqRegInst()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp264 .addReg(FrameReg, getKillRegState(FrameRegIsKill)) in eliminateFrameIndex()
279 .addReg(FrameReg, getKillRegState(FrameRegIsKill)) in eliminateFrameIndex()
286 .addReg(FrameReg, getKillRegState(FrameRegIsKill)) in eliminateFrameIndex()
H A DRISCVInstrInfo.cpp126 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
216 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
232 getKillRegState(KillSrc)); in copyPhysReg()
237 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
238 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
314 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
329 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp112 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
133 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) in copyPhysReg()
139 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
180 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
314 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStack()
753 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); in expandPseudoMTLoHi()
754 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); in expandPseudoMTLoHi()
764 unsigned KillSrc = getKillRegState(Src.isKill()); in expandCvtFPInt()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp79 unsigned Reg128Killed = getKillRegState(LowRegOp.isKill()); in splitMove()
263 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc)); in emitGRX32Move()
268 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc)) in emitGRX32Move()
785 .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit)); in copyPhysReg()
806 .addReg(SrcRegHi, getKillRegState(KillSrc)) in copyPhysReg()
807 .addReg(SrcRegLo, getKillRegState(KillSrc)); in copyPhysReg()
822 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1); in copyPhysReg()
831 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
859 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
873 .addReg(SrcReg, getKillRegState(isKill)), in storeRegToStackSlot()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp694 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()
695 .addReg(cmpOp2, getKillRegState(MO2IsKill)) in runOnMachineFunction()
700 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()

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