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Searched refs:dpm_table (Results 1 – 19 of 19) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_vega12_hwmgr.c524 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega12_setup_single_dpm_table() argument
534 dpm_table->count = num_of_levels; in vega12_setup_single_dpm_table()
541 dpm_table->dpm_levels[i].value = clk; in vega12_setup_single_dpm_table()
542 dpm_table->dpm_levels[i].enabled = true; in vega12_setup_single_dpm_table()
561 struct vega12_single_dpm_table *dpm_table; in vega12_setup_default_dpm_tables() local
564 memset(&data->dpm_table, 0, sizeof(data->dpm_table)); in vega12_setup_default_dpm_tables()
567 dpm_table = &(data->dpm_table.soc_table); in vega12_setup_default_dpm_tables()
569 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK); in vega12_setup_default_dpm_tables()
574 dpm_table->count = 1; in vega12_setup_default_dpm_tables()
575 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100; in vega12_setup_default_dpm_tables()
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H A Damdgpu_vega20_hwmgr.c570 struct vega20_single_dpm_table *dpm_table, PPCLK_e clk_id) in vega20_setup_single_dpm_table() argument
580 dpm_table->count = num_of_levels; in vega20_setup_single_dpm_table()
587 dpm_table->dpm_levels[i].value = clk; in vega20_setup_single_dpm_table()
588 dpm_table->dpm_levels[i].enabled = true; in vega20_setup_single_dpm_table()
598 struct vega20_single_dpm_table *dpm_table; in vega20_setup_gfxclk_dpm_table() local
601 dpm_table = &(data->dpm_table.gfx_table); in vega20_setup_gfxclk_dpm_table()
603 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK); in vega20_setup_gfxclk_dpm_table()
608 dpm_table->count = 1; in vega20_setup_gfxclk_dpm_table()
609 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100; in vega20_setup_gfxclk_dpm_table()
619 struct vega20_single_dpm_table *dpm_table; in vega20_setup_memclk_dpm_table() local
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H A Damdgpu_vega10_hwmgr.c1235 struct vega10_single_dpm_table *dpm_table, in vega10_setup_default_single_dpm_table() argument
1240 dpm_table->count = 0; in vega10_setup_default_single_dpm_table()
1243 if (i == 0 || dpm_table->dpm_levels[dpm_table->count - 1].value <= in vega10_setup_default_single_dpm_table()
1245 dpm_table->dpm_levels[dpm_table->count].value = in vega10_setup_default_single_dpm_table()
1247 dpm_table->dpm_levels[dpm_table->count].enabled = true; in vega10_setup_default_single_dpm_table()
1248 dpm_table->count++; in vega10_setup_default_single_dpm_table()
1255 struct vega10_pcie_table *pcie_table = &(data->dpm_table.pcie_table); in vega10_setup_default_pcie_table()
1306 struct vega10_single_dpm_table *dpm_table; in vega10_setup_default_dpm_tables() local
1348 dpm_table = &(data->dpm_table.soc_table); in vega10_setup_default_dpm_tables()
1350 dpm_table, in vega10_setup_default_dpm_tables()
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H A Damdgpu_smu7_hwmgr.c563 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, in smu7_setup_default_pcie_table()
574 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, in smu7_setup_default_pcie_table()
580 data->dpm_table.pcie_speed_table.count = max_entry - 1; in smu7_setup_default_pcie_table()
584 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, in smu7_setup_default_pcie_table()
589 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, in smu7_setup_default_pcie_table()
594 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, in smu7_setup_default_pcie_table()
599 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, in smu7_setup_default_pcie_table()
604 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, in smu7_setup_default_pcie_table()
609 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, in smu7_setup_default_pcie_table()
615 data->dpm_table.pcie_speed_table.count = 6; in smu7_setup_default_pcie_table()
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H A Damdgpu_smu_helper.c355 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_reset_single_dpm_table() local
357 dpm_table->count = count > max ? max : count; in phm_reset_single_dpm_table()
359 for (i = 0; i < dpm_table->count; i++) in phm_reset_single_dpm_table()
360 dpm_table->dpm_level[i].enabled = false; in phm_reset_single_dpm_table()
370 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_setup_pcie_table_entry() local
371 dpm_table->dpm_level[index].value = pcie_gen; in phm_setup_pcie_table_entry()
372 dpm_table->dpm_level[index].param1 = pcie_lanes; in phm_setup_pcie_table_entry()
373 dpm_table->dpm_level[index].enabled = 1; in phm_setup_pcie_table_entry()
380 struct vi_dpm_table *dpm_table = (struct vi_dpm_table *)table; in phm_get_dpm_level_enable_mask_value() local
382 for (i = dpm_table->count; i > 0; i--) { in phm_get_dpm_level_enable_mask_value()
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H A Dsmu7_hwmgr.h206 struct smu7_dpm_table dpm_table; member
H A Dvega12_hwmgr.h316 struct vega12_dpm_table dpm_table; member
H A Dvega10_hwmgr.h313 struct vega10_dpm_table dpm_table; member
H A Dvega20_hwmgr.h439 struct vega20_dpm_table dpm_table; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
H A Damdgpu_vega20_ppt.c726 struct vega20_dpm_table *dpm_table = NULL; in vega20_set_default_dpm_table() local
729 dpm_table = smu_dpm->dpm_context; in vega20_set_default_dpm_table()
732 single_dpm_table = &(dpm_table->soc_table); in vega20_set_default_dpm_table()
748 single_dpm_table = &(dpm_table->gfx_table); in vega20_set_default_dpm_table()
764 single_dpm_table = &(dpm_table->mem_table); in vega20_set_default_dpm_table()
780 single_dpm_table = &(dpm_table->eclk_table); in vega20_set_default_dpm_table()
795 single_dpm_table = &(dpm_table->vclk_table); in vega20_set_default_dpm_table()
810 single_dpm_table = &(dpm_table->dclk_table); in vega20_set_default_dpm_table()
825 single_dpm_table = &(dpm_table->dcef_table); in vega20_set_default_dpm_table()
841 single_dpm_table = &(dpm_table->pixel_table); in vega20_set_default_dpm_table()
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H A Damdgpu_arcturus_ppt.c426 struct arcturus_dpm_table *dpm_table = NULL; in arcturus_set_default_dpm_table() local
429 dpm_table = smu_dpm->dpm_context; in arcturus_set_default_dpm_table()
432 single_dpm_table = &(dpm_table->soc_table); in arcturus_set_default_dpm_table()
447 single_dpm_table = &(dpm_table->gfx_table); in arcturus_set_default_dpm_table()
462 single_dpm_table = &(dpm_table->mem_table); in arcturus_set_default_dpm_table()
477 single_dpm_table = &(dpm_table->fclk_table); in arcturus_set_default_dpm_table()
491 memcpy(smu_dpm->golden_dpm_context, dpm_table, in arcturus_set_default_dpm_table()
572 struct arcturus_dpm_table *dpm_table = NULL; in arcturus_populate_umd_state_clk() local
576 dpm_table = smu_dpm->dpm_context; in arcturus_populate_umd_state_clk()
577 gfx_table = &(dpm_table->gfx_table); in arcturus_populate_umd_state_clk()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_fiji_smumgr.c497 SMU73_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in fiji_populate_bapm_parameters_in_dpm_table() local
509 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
511 dpm_table->TargetTdp = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
518 dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp); in fiji_populate_bapm_parameters_in_dpm_table()
519 dpm_table->GpuTjHyst = 8; in fiji_populate_bapm_parameters_in_dpm_table()
521 dpm_table->DTEAmbientTempBase = defaults->DTEAmbientTempBase; in fiji_populate_bapm_parameters_in_dpm_table()
524 dpm_table->TemperatureLimitEdge = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
526 dpm_table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
528 dpm_table->TemperatureLimitLiquid1 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
530 dpm_table->TemperatureLimitLiquid2 = PP_HOST_TO_SMC_US( in fiji_populate_bapm_parameters_in_dpm_table()
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H A Damdgpu_iceland_smumgr.c772 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_smc_link_level() local
777 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in iceland_populate_smc_link_level()
779 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in iceland_populate_smc_link_level()
781 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
793 (uint8_t)dpm_table->pcie_speed_table.count; in iceland_populate_smc_link_level()
795 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in iceland_populate_smc_link_level()
968 struct smu7_dpm_table *dpm_table = &data->dpm_table; in iceland_populate_all_graphic_levels() local
985 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
987 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
1001 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
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H A Damdgpu_ci_smumgr.c479 struct smu7_dpm_table *dpm_table = &data->dpm_table; in ci_populate_all_graphic_levels() local
489 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
491 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
497 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
504 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
506 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
723 SMU7_Discrete_DpmTable *dpm_table = &(smu_data->smc_state_table); in ci_populate_bapm_parameters_in_dpm_table() local
729 dpm_table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 256)); in ci_populate_bapm_parameters_in_dpm_table()
730 dpm_table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usConfigurableTDP * 256)); in ci_populate_bapm_parameters_in_dpm_table()
732 dpm_table->DTETjOffset = 0; in ci_populate_bapm_parameters_in_dpm_table()
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H A Damdgpu_vegam_smumgr.c578 struct smu7_dpm_table *dpm_table = &data->dpm_table; in vegam_populate_smc_link_level() local
583 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in vegam_populate_smc_link_level()
585 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in vegam_populate_smc_link_level()
587 dpm_table->pcie_speed_table.dpm_levels[i].param1); in vegam_populate_smc_link_level()
595 (uint8_t)dpm_table->pcie_speed_table.count; in vegam_populate_smc_link_level()
599 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in vegam_populate_smc_link_level()
870 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in vegam_populate_all_graphic_levels() local
874 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in vegam_populate_all_graphic_levels()
890 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels()
893 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
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H A Damdgpu_tonga_smumgr.c515 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_smc_link_level() local
520 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in tonga_populate_smc_link_level()
522 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in tonga_populate_smc_link_level()
524 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in tonga_populate_smc_link_level()
536 (uint8_t)dpm_table->pcie_speed_table.count; in tonga_populate_smc_link_level()
538 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in tonga_populate_smc_link_level()
696 struct smu7_dpm_table *dpm_table = &data->dpm_table; in tonga_populate_all_graphic_levels() local
698 uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count; in tonga_populate_all_graphic_levels()
715 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
717 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
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H A Damdgpu_polaris10_smumgr.c776 struct smu7_dpm_table *dpm_table = &data->dpm_table; in polaris10_populate_smc_link_level() local
781 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) { in polaris10_populate_smc_link_level()
783 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value; in polaris10_populate_smc_link_level()
785 dpm_table->pcie_speed_table.dpm_levels[i].param1); in polaris10_populate_smc_link_level()
793 (uint8_t)dpm_table->pcie_speed_table.count; in polaris10_populate_smc_link_level()
797 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table); in polaris10_populate_smc_link_level()
986 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table; in polaris10_populate_all_graphic_levels() local
990 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count; in polaris10_populate_all_graphic_levels()
1006 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
1009 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_ci_dpm.c439 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table() local
447 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
448 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256; in ci_populate_bapm_parameters_in_dpm_table()
450 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
451 dpm_table->GpuTjMax = in ci_populate_bapm_parameters_in_dpm_table()
453 dpm_table->GpuTjHyst = 8; in ci_populate_bapm_parameters_in_dpm_table()
455 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base; in ci_populate_bapm_parameters_in_dpm_table()
458 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000); in ci_populate_bapm_parameters_in_dpm_table()
459 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256); in ci_populate_bapm_parameters_in_dpm_table()
461 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0); in ci_populate_bapm_parameters_in_dpm_table()
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H A Dci_dpm.h197 struct ci_dpm_table dpm_table; member