Home
last modified time | relevance | path

Searched refs:ctrl_reg (Results 1 – 6 of 6) sorted by relevance

/netbsd-src/sys/arch/arm/sunxi/
H A Dsunxi_nmi.c65 bus_size_t ctrl_reg; member
72 .ctrl_reg = 0x00,
79 .ctrl_reg = 0x0c,
86 .ctrl_reg = 0x00,
152 val = NMI_READ(sc, sc->sc_config->ctrl_reg); in sunxi_nmi_irq_set_type()
155 NMI_WRITE(sc, sc->sc_config->ctrl_reg, val); in sunxi_nmi_irq_set_type()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gt/
H A Dintel_engine_types.h172 bus_size_t ctrl_reg; member
185 u32 __iomem *ctrl_reg; member
H A Dintel_lrc.c1417 if (execlists->ctrl_reg) { in write_desc()
1425 if (execlists->ctrl_reg) { in write_desc()
1564 if (execlists->ctrl_reg) in execlists_submit_ports()
1566 bus_space_write_4(execlists->bst, execlists->bsh, execlists->ctrl_reg, EL_CTRL_LOAD); in execlists_submit_ports()
1568 writel(EL_CTRL_LOAD, execlists->ctrl_reg); in execlists_submit_ports()
4419 execlists->ctrl_reg = i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base)); in intel_execlists_submission_setup()
4425 execlists->ctrl_reg = uncore->regs + in intel_execlists_submission_setup()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dvlv_dsi.c136 i915_reg_t data_reg, ctrl_reg; in intel_dsi_host_transfer() local
149 ctrl_reg = MIPI_LP_GEN_CTRL(port); in intel_dsi_host_transfer()
154 ctrl_reg = MIPI_HS_GEN_CTRL(port); in intel_dsi_host_transfer()
177 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); in intel_dsi_host_transfer()
985 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? in intel_dsi_get_hw_state() local
987 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; in intel_dsi_get_hw_state()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gvt/
H A Dcmd_parser.c1204 i915_reg_t ctrl_reg; member
1250 info->ctrl_reg = DSPCNTR(info->pipe); in gen8_decode_mi_display_flip()
1254 info->ctrl_reg = SPRCTL(info->pipe); in gen8_decode_mi_display_flip()
1316 info->ctrl_reg = DSPCNTR(info->pipe); in skl_decode_mi_display_flip()
1334 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & in gen8_check_mi_display_flip()
1339 tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10; in gen8_check_mi_display_flip()
1363 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10), in gen8_update_plane_mmio_from_mi_display_flip()
1368 set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10), in gen8_update_plane_mmio_from_mi_display_flip()
/netbsd-src/sys/dev/ic/
H A Dadvlib.c1460 u_int8_t ctrl_reg; in AscISR() local
1469 ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh); in AscISR()
1470 saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET | in AscISR()
1499 (ctrl_reg & ASC_CC_SINGLE_STEP)) { in AscISR()