| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsLegalizerInfo.cpp | 410 MIRBuilder.buildMerge(Val, {Load_P2Half, Load_Rem}); in legalizeCustom()
412 auto Merge = MIRBuilder.buildMerge(s64, {Load_P2Half, Load_Rem}); in legalizeCustom()
439 auto Bitcast = MIRBuilder.buildMerge(s64, {Src, C_HiMask.getReg(0)}); in legalizeCustom()
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| H A D | MipsCallLowering.cpp | 148 MIRBuilder.buildMerge(ValVReg, {Lo, Hi}); in assignValueToReg()
209 MIRBuilder.buildMerge(ArgsReg, VRegs); in handleSplit()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 360 B.buildMerge(OrigRegs[0], Regs); in buildCopyFromRegs()
362 auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs); in buildCopyFromRegs()
430 auto Merge = B.buildMerge(RealDstEltTy, Regs.take_front(PartsPerElt)); in buildCopyFromRegs()
499 UnmergeSrc = B.buildMerge(LCMTy, MergeParts).getReg(0); in buildCopyToRegs()
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| H A D | LegalizerHelper.cpp | 208 MIRBuilder.buildMerge(DstReg, PartRegs); in insertParts()
358 Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0); in buildLCMMergePieces()
377 MIRBuilder.buildMerge(DstReg, RemergeRegs); in buildWidenedRemergeToDst()
381 auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs); in buildWidenedRemergeToDst()
395 MIRBuilder.buildMerge(LCMTy, RemergeRegs)); in buildWidenedRemergeToDst()
820 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
1050 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); in narrowScalar()
1184 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
1204 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); in narrowScalar()
1441 auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD)); in widenScalarMergeValues()
[all …]
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| H A D | MachineIRBuilder.cpp | 568 buildMerge(Res, Ops); in buildSequence()
588 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res, in buildMerge() function in MachineIRBuilder
599 MachineIRBuilder::buildMerge(const DstOp &Res, in buildMerge() function in MachineIRBuilder
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| H A D | CombinerHelper.cpp | 336 Builder.buildMerge(NewDstReg, Ops); in applyCombineShuffleVector()
2224 Builder.buildMerge(DstReg, { Narrowed, Zero }); in applyCombineShiftToUnmerge()
2237 Builder.buildMerge(DstReg, { Zero, Narrowed }); in applyCombineShiftToUnmerge()
2247 Builder.buildMerge(DstReg, { Unmerge.getReg(1), Hi }); in applyCombineShiftToUnmerge()
2253 Builder.buildMerge(DstReg, { Hi, Hi }); in applyCombineShiftToUnmerge()
2261 Builder.buildMerge(DstReg, { Lo, Hi }); in applyCombineShiftToUnmerge()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 1832 B.buildMerge(Dst, {Src, HighAddr}); in legalizeAddrSpaceCast()
1879 auto BuildPtr = B.buildMerge(DstTy, {SrcAsInt, ApertureReg}); in legalizeAddrSpaceCast()
2003 auto SignBit64 = B.buildMerge(S64, {Zero32, SignBit}); in legalizeIntrinsicTrunc()
2079 B.buildMerge(Dst, { Lo, Hi }); in legalizeFPTOI()
2662 auto Merge = B.buildMerge(S32, {Src0, Src1}); in legalizeBuildVector()
2891 auto Rcp = B.buildMerge(S64, {RcpLo, RcpHi}); in legalizeUDIV_UREM64Impl()
2906 auto Add1 = B.buildMerge(S64, {Add1_Lo, Add1_Hi}); in legalizeUDIV_UREM64Impl()
2919 auto Add2 = B.buildMerge(S64, {Add2_Lo, Add2_Hi}); in legalizeUDIV_UREM64Impl()
2933 auto Sub1 = B.buildMerge(S64, {Sub1_Lo, Sub1_Hi}); in legalizeUDIV_UREM64Impl()
2956 auto Sub2 = B.buildMerge(S64, {Sub2_Lo, Sub2_Hi}); in legalizeUDIV_UREM64Impl()
[all …]
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| H A D | AMDGPURegisterBankInfo.cpp | 933 B.buildMerge(LLT::scalar(64), in executeInWaterfallLoop()
988 auto Merge = B.buildMerge(OpTy, ReadlanePieces); in executeInWaterfallLoop()
1524 B.buildMerge(Dst, LoadParts); in applyMappingSBufferLoad()
1666 return B.buildMerge(LLT::vector(NumElts, S32), WideRegs).getReg(0); in handleD16VData()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 288 Builder.buildMerge(DstReg, SrcRegs); in tryCombineTrunc()
689 Builder.buildMerge(DefReg, Regs); in tryCombineUnmergeValues()
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| H A D | MachineIRBuilder.h | 931 MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);
932 MachineInstrBuilder buildMerge(const DstOp &Res,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86CallLowering.cpp | 383 MIRBuilder.buildMerge(Info.OrigRet.Regs[0], NewRegs); in lowerCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 338 MIRBuilder.buildMerge(Arg.Regs[0], NewRegs); in assignCustomValue()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 410 MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef}).getReg(0); in lowerReturn()
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| H A D | AArch64LegalizerInfo.cpp | 1142 MIRBuilder.buildMerge(MI.getOperand(0), {DstLo, DstHi}); in legalizeAtomicCmpxchg128()
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