| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 919 void addRegOperands(MCInst &Inst, unsigned N) const;
922 addRegOperands(Inst, N); in addBoolRegOperands()
927 addRegOperands(Inst, N); in addRegOrImmOperands()
938 addRegOperands(Inst, N); in addRegOrImmWithInputModsOperands()
958 addRegOperands(Inst, N); in addRegWithInputModsOperands()
2153 void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in AMDGPUOperand
5834 Op.addRegOperands(Inst, 1); in cvtDSOffset01()
5858 Op.addRegOperands(Inst, 1); in cvtDSImpl()
5899 Op.addRegOperands(Inst, 1); in cvtExp()
6991 Op.addRegOperands(Inst, 1); in cvtMubufImpl()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 175 let RenderMethod = "addRegOperands";
648 let RenderMethod = "addRegOperands";
697 let RenderMethod = "addRegOperands", ParserMethod="tryParseGPRSeqPair" in {
731 let RenderMethod = "addRegOperands";
877 let RenderMethod = "addRegOperands";
928 let RenderMethod = "addRegOperands";
1087 let RenderMethod = "addRegOperands";
1145 let RenderMethod = "addRegOperands";
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/AsmParser/ |
| H A D | M68kAsmParser.cpp | 153 void addRegOperands(MCInst &Inst, unsigned N) const;
259 void M68kOperand::addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in M68kOperand
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 188 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 260 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/AsmParser/ |
| H A D | MSP430AsmParser.cpp | 125 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon2a5e3db90111::MSP430Operand
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 295 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anond0f948490111::SystemZOperand
1306 ZOperand.addRegOperands(Inst, 1); in ParseDirectiveInsn()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 517 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/AsmParser/ |
| H A D | AVRAsmParser.cpp | 130 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon484a835d0111::AVROperand
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.td | 41 let RenderMethod = "addRegOperands";
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoA.td | 22 let RenderMethod = "addRegOperands";
|
| H A D | RISCVInstrInfoV.td | 36 let RenderMethod = "addRegOperands";
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/AsmParser/ |
| H A D | WebAssemblyAsmParser.cpp | 115 void addRegOperands(MCInst &, unsigned) const { in addRegOperands() function
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 402 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.td | 96 let RenderMethod = "addRegOperands";
108 let RenderMethod = "addRegOperands";
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 370 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon6f8db8bd0211::SparcOperand
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 462 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anonf0f8b3610211::VEOperand
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2539 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anonad70014b0111::ARMOperand
5738 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5747 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5816 ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt in cvtMVEVMOVQtoDReg()
5817 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2 in cvtMVEVMOVQtoDReg()
5818 ((ARMOperand &)*Operands[4]).addRegOperands(Inst, 1); // Qd in cvtMVEVMOVQtoDReg()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 441 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 382 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 823 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.td | 960 let RenderMethod = "addRegOperands";
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1483 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon65f0dadd0111::AArch64Operand
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 1058 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon5ed6d99d0211::MipsOperand
|