Searched refs:UseOp (Results 1 – 8 of 8) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCPreEmitPeephole.cpp | 291 const MachineOperand *UseOp = in addLinkerOpt() local
295 if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg && in addLinkerOpt()
296 UseOp->isUse() && UseOp->isKill()) { in addLinkerOpt()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineTraceMetrics.cpp | 630 unsigned UseOp; member
632 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) in DataDep()
633 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
636 DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp) in DataDep()
637 : UseOp(UseOp) { in DataDep()
804 .computeOperandLatency(Dep.DefMI, Dep.DefOp, &UseMI, Dep.UseOp); in updateDepth()
960 Dep.UseOp); in pushDepHeight()
1192 &PHI, Dep.UseOp); in getPHIDepth()
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| H A D | ScheduleDAGInstrs.cpp | 254 int UseOp = I->OpIdx; in addPhysRegDataDeps() local
257 if (UseOp < 0) in addPhysRegDataDeps()
269 (UseMIDesc && UseOp >= ((int)UseMIDesc->getNumOperands()) && in addPhysRegDataDeps()
273 RegUse, UseOp)); in addPhysRegDataDeps()
274 ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep); in addPhysRegDataDeps()
280 ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOp, Dep); in addPhysRegDataDeps()
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| H A D | ModuloSchedule.cpp | 87 MachineOperand &UseOp = *UI; in expand() local
88 MachineInstr *UseMI = UseOp.getParent(); in expand()
1151 MachineOperand &UseOp = *UI; in rewriteScheduledInstr() local
1152 MachineInstr *UseMI = UseOp.getParent(); in rewriteScheduledInstr()
1189 UseOp.setReg(ReplaceReg); in rewriteScheduledInstr()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 566 MachineOperand &UseOp = UseMI->getOperand(UseOpIdx); in tryToFoldACImm() local
567 if (!UseOp.getSubReg() && Def && TII->isFoldableCopy(*Def)) { in tryToFoldACImm()
609 const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx); in foldOperand() local
611 if (!isUseSafeToFold(TII, *UseMI, UseOp)) in foldOperand()
615 if (UseOp.isReg() && OpToFold.isReg()) { in foldOperand()
616 if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister) in foldOperand()
895 UseOp.isImplicit() || in foldOperand()
915 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) { in foldOperand()
916 Register UseReg = UseOp.getReg(); in foldOperand()
923 if (UseOp.getSubReg() == AMDGPU::sub0) { in foldOperand()
[all …]
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| H A D | AMDGPUAsmPrinter.cpp | 684 for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) { in hasAnyNonFlatUseOfReg() local
685 if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent())) in hasAnyNonFlatUseOfReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 5236 int UseOp = -1; in getPartialRegUpdateClearance() local
5248 UseOp = MI.findRegisterUseOperandIdx(Reg, false, TRI); in getPartialRegUpdateClearance()
5253 UseOp = 3; in getPartialRegUpdateClearance()
5261 if (UseOp != -1 && MI.getOperand(UseOp).readsReg()) in getPartialRegUpdateClearance()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 10357 SDValue UseOp = User->getOperand(i); in ExtendUsesToFormExtLoad() local
10358 if (UseOp == N0) in ExtendUsesToFormExtLoad()
10360 if (!isa<ConstantSDNode>(UseOp)) in ExtendUsesToFormExtLoad()
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