| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 41 UXTH, enumerator
61 case AArch64_AM::UXTH: return "uxth"; in getShiftExtendName()
128 case 1: return AArch64_AM::UXTH; in getExtendType()
155 case AArch64_AM::UXTH: return 1; break; in getExtendEncoding()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 474 UXTH, enumerator
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredicates.td | 19 def CheckExtUXTH : CheckImmOperand_s<3, "AArch64_AM::UXTH">;
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| H A D | AArch64ExpandPseudoInsts.cpp | 1083 AArch64_AM::getArithExtendImm(AArch64_AM::UXTH, 0), in expandMI()
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| H A D | AArch64ISelDAGToDAG.cpp | 574 return AArch64_AM::UXTH; in getExtendTypeForNode()
592 return !IsLoadStore ? AArch64_AM::UXTH : AArch64_AM::InvalidShiftExtend; in getExtendTypeForNode()
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| H A D | AArch64InstrInfo.cpp | 912 case AArch64_AM::UXTH: in isFalkorShiftExtFast()
946 case AArch64_AM::UXTH: in isFalkorShiftExtFast()
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| H A D | AArch64FastISel.cpp | 1154 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH; in emitAddSub()
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| /netbsd-src/sys/external/bsd/sljit/dist/sljit_src/ |
| H A D | sljitNativeARM_T2_32.c | 168 #define UXTH 0xb280 macro
718 return push_inst16(compiler, UXTH | RD3(dst) | RN3(arg2)); in emit_op_imm()
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| H A D | sljitNativeARM_32.c | 125 #define UXTH 0xe6ff0070 macro
1039 return push_inst(compiler, (op == SLJIT_MOV_U16 ? UXTH : SXTH) | RD(dst) | RM(src2)); in emit_single_op()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 301 STORE_OPCODE(ZEXT16, UXTH); in OpcodeCache()
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| H A D | ARMFastISel.cpp | 2658 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } } in ARMEmitIntExt()
2898 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 },
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| H A D | ARMScheduleSwift.td | 161 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| H A D | ARMScheduleR52.td | 215 (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
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| H A D | ARMScheduleA57.td | 361 // Sign/zero extend, normal: SXTB, SXTH, UXTB, UXTH
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| H A D | ARMInstrThumb.td | 1775 // restrict the register class for the UXTB/UXTH ops used in the expansion.
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| H A D | ARMInstrInfo.td | 3738 def UXTH : AI_ext_rrot<0b01101111,
6081 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
6225 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
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| H A D | ARMExpandPseudoInsts.cpp | 2853 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, ARM::UXTH, in ExpandMI()
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/ |
| H A D | types.md | 60 ; extend extend instruction (SXTB, SXTH, UXTB, UXTH).
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/ |
| H A D | types.md | 78 ; extend extend instruction (SXTB, SXTH, UXTB, UXTH).
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1310 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend()
1323 ET == AArch64_AM::UXTH || ET == AArch64_AM::SXTH || in isExtend64()
2827 .Case("uxth", AArch64_AM::UXTH) in tryParseOptionalShiftExtend()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 5777 return AArch64_AM::UXTH; in getExtendTypeForInst()
5800 return !IsLoadStore ? AArch64_AM::UXTH : AArch64_AM::InvalidShiftExtend; in getExtendTypeForInst()
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/aarch64/ |
| H A D | aarch64-sve.md | 3044 ;; - UXTH
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/aarch64/ |
| H A D | aarch64-sve.md | 3063 ;; - UXTH
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