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Searched refs:TmpVGPR (Results 1 – 2 of 2) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFrameLowering.cpp799 MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister( in emitPrologue() local
801 if (!TmpVGPR) in emitPrologue()
804 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR) in emitPrologue()
807 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, TmpVGPR, in emitPrologue()
817 MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister( in emitPrologue() local
819 if (!TmpVGPR) in emitPrologue()
822 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR) in emitPrologue()
825 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, TmpVGPR, in emitPrologue()
1014 MCPhysReg TmpVGPR = findScratchNonCalleeSaveRegister( in emitEpilogue() local
1016 if (!TmpVGPR) in emitEpilogue()
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H A DSIRegisterInfo.cpp88 Register TmpVGPR = AMDGPU::NoRegister; member
166 TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0, false); in prepare()
170 if (TmpVGPR) { in prepare()
176 TmpVGPR = AMDGPU::VGPR0; in prepare()
195 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
206 I.addReg(TmpVGPR, RegState::ImplicitDefine); in prepare()
232 I.addReg(TmpVGPR, RegState::ImplicitKill); in restore()
240 I.addReg(TmpVGPR, RegState::ImplicitKill); in restore()
1292 buildSpillLoadStore(SB.MBB, SB.MI, Opc, Index, SB.TmpVGPR, false, FrameReg, in buildVGPRSpillLoadStore()
1297 buildSpillLoadStore(SB.MBB, SB.MI, Opc, Index, SB.TmpVGPR, IsKill, FrameReg, in buildVGPRSpillLoadStore()
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