Searched refs:TargetReg (Results 1 – 8 of 8) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 186 unsigned TargetReg = Inst.getOperand(1).getReg(); in emitInstruction() local
187 emitMask(TargetReg, IndirectBranchMaskReg, STI); in emitInstruction()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86SpeculativeLoadHardening.cpp | 993 unsigned TargetReg; in tracePredStateThroughIndirectBranches() local
1024 TargetReg = TI.getOperand(0).getReg(); in tracePredStateThroughIndirectBranches()
1044 TargetAddrSSA.AddAvailableValue(&MBB, TargetReg); in tracePredStateThroughIndirectBranches()
1111 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches() local
1116 TII->get(X86::MOV64ri32), TargetReg) in tracePredStateThroughIndirectBranches()
1124 TargetReg) in tracePredStateThroughIndirectBranches()
1136 TargetAddrSSA.AddAvailableValue(Pred, TargetReg); in tracePredStateThroughIndirectBranches()
1144 unsigned TargetReg = TargetAddrSSA.GetValueInMiddleOfBlock(&MBB); in tracePredStateThroughIndirectBranches() local
1155 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
1174 .addReg(TargetReg, RegState::Kill) in tracePredStateThroughIndirectBranches()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 161 Register TargetReg) { in buildGitPtr() argument
166 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); in buildGitPtr()
167 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr()
172 .addReg(TargetReg, RegState::ImplicitDefine); in buildGitPtr()
175 BuildMI(MBB, I, DL, GetPC64, TargetReg); in buildGitPtr()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.cpp | 896 Register TargetReg = I->getOperand(1).getReg(); in expandEhReturn() local
904 .addReg(TargetReg) in expandEhReturn()
907 .addReg(TargetReg) in expandEhReturn()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2960 Register TargetReg = MI.getOperand(0).getReg(); in expandVSXMemPseudo() local
2962 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo()
2963 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) in expandVSXMemPseudo()
3047 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
3048 if (PPC::VSFRCRegClass.contains(TargetReg)) { in expandPostRAPseudo()
3069 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
3070 if (PPC::VSFRCRegClass.contains(TargetReg)) in expandPostRAPseudo()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 214 const SmallSet<Register, 2> &TargetReg,
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3283 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectBrJT() local
3288 {TargetReg, ScratchReg}, {JTAddr, Index}) in selectBrJT()
3291 MIB.buildInstr(AArch64::BR, {}, {TargetReg}); in selectBrJT()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 2625 Register TargetReg, Register InsertReg, in buildBitFieldInsert() argument
2627 LLT TargetTy = B.getMRI()->getType(TargetReg); in buildBitFieldInsert()
2641 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); in buildBitFieldInsert()
|