| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/Stages/ |
| H A D | Stage.h | 27 class Stage {
28 Stage *NextInSequence;
31 Stage(const Stage &Other) = delete;
32 Stage &operator=(const Stage &Other) = delete;
38 Stage() : NextInSequence(nullptr) {} in Stage() function
39 virtual ~Stage();
57 void setNextInSequence(Stage *NextStage) { in setNextInSequence()
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| H A D | InstructionTables.h | 28 class InstructionTables final : public Stage {
35 : Stage(), SM(Model), Masks(Model.getNumProcResourceKinds()) { in InstructionTables()
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| H A D | RetireStage.h | 28 class RetireStage final : public Stage {
39 : Stage(), RCU(R), PRF(F), LSU(LS) {} in RetireStage()
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| H A D | ExecuteStage.h | 28 class ExecuteStage final : public Stage {
52 : Stage(), HWS(S), NumDispatchedOpcodes(0), NumIssuedOpcodes(0), in ExecuteStage()
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| H A D | EntryStage.h | 26 class EntryStage final : public Stage {
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| H A D | DispatchStage.h | 49 class DispatchStage final : public Stage {
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| H A D | MicroOpQueueStage.h | 26 class MicroOpQueueStage : public Stage {
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| H A D | InOrderIssueStage.h | 31 class InOrderIssueStage final : public Stage {
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/ |
| H A D | Instruction.cpp | 152 assert(Stage == IS_INVALID); in dispatch()
153 Stage = IS_DISPATCHED; in dispatch()
162 assert(Stage == IS_READY); in execute()
163 Stage = IS_EXECUTING; in execute()
173 Stage = IS_EXECUTED; in execute()
177 assert(Stage == IS_READY && "Invalid internal state!"); in forceExecuted()
179 Stage = IS_EXECUTED; in forceExecuted()
192 Stage = IS_READY; in updatePending()
209 Stage = IS_PENDING; in updateDispatched()
241 Stage = IS_EXECUTED; in cycleEvent()
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| H A D | Pipeline.cpp | 32 return any_of(Stages, [](const std::unique_ptr<Stage> &S) { in hasWorkToProcess()
55 const std::unique_ptr<Stage> &S = *I; in runCycle()
61 Stage &FirstStage = *Stages[0]; in runCycle()
66 for (const std::unique_ptr<Stage> &S : Stages) { in runCycle()
75 void Pipeline::appendStage(std::unique_ptr<Stage> S) { in appendStage()
78 Stage *Last = Stages.back().get(); in appendStage()
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| H A D | CMakeLists.txt | 21 Stages/Stage.cpp
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ModuloSchedule.h | 92 DenseMap<MachineInstr *, int> Stage; variable
108 DenseMap<MachineInstr *, int> Stage) in ModuloSchedule() argument
110 Stage(std::move(Stage)) { in ModuloSchedule()
112 for (auto &KV : this->Stage) in ModuloSchedule()
134 auto I = Stage.find(MI); in getStage()
135 return I == Stage.end() ? -1 : I->second; in getStage()
146 assert(Stage.count(MI) == 0); in setStage()
147 Stage[MI] = MIStage; in setStage()
340 MachineBasicBlock *SourceBB, unsigned Stage);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | GCNSchedStrategy.cpp | 306 MinOccupancy(StartingOccupancy), Stage(Collect), RegionIdx(0) { in GCNScheduleDAGMILive()
312 if (Stage == Collect) { in schedule()
339 S.HasClusteredNodes = Stage > InitialSchedule; in schedule()
344 if (Stage == InitialSchedule && S.HasClusteredNodes) in schedule()
398 if (Stage == UnclusteredReschedule && in schedule()
406 (Stage + 1) == UnclusteredReschedule) in schedule()
416 (Stage + 1) != UnclusteredReschedule; in schedule()
561 Stage++; in finalizeSchedule()
565 if (Stage > InitialSchedule) { in finalizeSchedule()
574 if (Stage == UnclusteredReschedule) { in finalizeSchedule()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/ |
| H A D | Stage.cpp | 21 Stage::~Stage() = default;
23 void Stage::addListener(HWEventListener *Listener) { in addListener()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 458 enum InstrStage Stage; variable
494 : InstructionBase(D), Stage(IS_INVALID), CyclesLeft(UNKNOWN_CYCLES), in Instruction()
528 bool isDispatched() const { return Stage == IS_DISPATCHED; } in isDispatched()
529 bool isPending() const { return Stage == IS_PENDING; } in isPending()
530 bool isReady() const { return Stage == IS_READY; } in isReady()
531 bool isExecuting() const { return Stage == IS_EXECUTING; } in isExecuting()
532 bool isExecuted() const { return Stage == IS_EXECUTED; } in isExecuted()
533 bool isRetired() const { return Stage == IS_RETIRED; } in isRetired()
542 Stage = IS_RETIRED; in retire()
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| H A D | Pipeline.h | 55 SmallVector<std::unique_ptr<Stage>, 8> Stages;
66 void appendStage(std::unique_ptr<Stage> S);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | ModuloSchedule.cpp | 1599 int Stage = getStage(MI); in filterInstructions() local
1600 if (Stage == -1 || Stage >= MinStage) in filterInstructions()
1624 MachineBasicBlock *DestBB, MachineBasicBlock *SourceBB, unsigned Stage) { in moveStageBetweenBlocks() argument
1632 if (getStage(MI) != Stage) { in moveStageBetweenBlocks()
1647 if (getStage(MI) != Stage) in moveStageBetweenBlocks()
1661 if (getStage(Def) == Stage) { in moveStageBetweenBlocks()
1778 unsigned Stage = Schedule.getNumStages() - 1 + I - J; in peelPrologAndEpilogs() local
1781 moveStageBetweenBlocks(Epilogs[K - 1], Epilogs[K], Stage); in peelPrologAndEpilogs()
1782 LS[Stage] = 1; in peelPrologAndEpilogs()
1911 int Stage = getStage(MI); in rewriteUsesOf() local
[all …]
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| H A D | RegAllocGreedy.cpp | 241 LiveRangeStage Stage = RS_New; member
252 return ExtraRegInfo[VirtReg.reg()].Stage; in getStage()
255 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
257 ExtraRegInfo[VirtReg.reg()].Stage = Stage; in setStage()
265 if (ExtraRegInfo[Reg].Stage == RS_New) in setStage()
266 ExtraRegInfo[Reg].Stage = NewStage; in setStage()
708 ExtraRegInfo[Old].Stage = RS_Assign; in LRE_DidCloneVirtReg()
730 if (ExtraRegInfo[Reg].Stage == RS_New) in enqueue()
731 ExtraRegInfo[Reg].Stage = RS_Assign; in enqueue()
733 if (ExtraRegInfo[Reg].Stage == RS_Split) { in enqueue()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/docker/nvidia-cuda/ |
| H A D | Dockerfile | 8 # Stage 1. Check out LLVM source code and run the build.
28 # Stage 2. Produce a minimal release image with build results.
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/docker/example/ |
| H A D | Dockerfile | 11 # Stage 1. Check out LLVM source code and run the build.
30 # Stage 2. Produce a minimal release image with build results.
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/docker/debian8/ |
| H A D | Dockerfile | 8 # Stage 1. Check out LLVM source code and run the build.
52 # Stage 2. Produce a minimal release image with build results.
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/Proposals/ |
| H A D | VectorPredication.rst | 73 lower to VP SDNodes (from Stage 2).
76 - InstCombine/InstSimplify expect predication in regular Instructions (Stage (3)
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/gn/secondary/llvm/lib/MCA/ |
| H A D | BUILD.gn | 29 "Stages/Stage.cpp",
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| /netbsd-src/external/apache2/llvm/lib/libLLVMMCA/ |
| H A D | Makefile | 35 Stage.cpp
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 435 unsigned Stage = II[SchedClass].LastStage - 1; in getCVIResources() local
439 return ((Stage + HexagonStages)->getUnits()); in getCVIResources()
464 for (unsigned Stage = II[SchedClass].FirstStage + 1; in getOtherReservedSlots() local
465 Stage < II[SchedClass].LastStage; ++Stage) { in getOtherReservedSlots()
466 unsigned Units = (Stage + HexagonStages)->getUnits(); in getOtherReservedSlots()
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