Searched refs:ShiftReg (Results 1 – 6 of 6) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 1499 Register ShiftReg = RI.createVirtualRegister(RC); in EmitShiftInstr() local
1519 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg) in EmitShiftInstr()
1530 .addReg(ShiftReg) in EmitShiftInstr()
1531 .addReg(ShiftReg); in EmitShiftInstr()
1534 .addReg(ShiftReg); in EmitShiftInstr()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1586 Register ShiftReg = RI.createVirtualRegister(RC); in insertShift() local
1598 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg); in insertShift()
1600 ShiftMI.addReg(ShiftReg); in insertShift()
1608 BuildMI(CheckBB, dl, TII.get(AVR::PHI), ShiftReg) in insertShift()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 1852 Register ShiftReg = I.getOperand(2).getReg(); in preISelLower() local
1853 const LLT ShiftTy = MRI.getType(ShiftReg); in preISelLower()
1860 auto *AmtMI = MRI.getVRegDef(ShiftReg); in preISelLower()
1865 .addReg(ShiftReg, 0, AArch64::sub_32); in preISelLower()
5736 Register ShiftReg = ShiftLHS.getReg(); in selectShiftedRegister() local
5738 unsigned NumBits = MRI.getType(ShiftReg).getSizeInBits(); in selectShiftedRegister()
5742 return {{[=](MachineInstrBuilder &MIB) { MIB.addUse(ShiftReg); }, in selectShiftedRegister()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 874 unsigned ShiftReg; member
1389 RegShiftedReg.ShiftReg); in isRegShiftedReg()
2549 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
3640 unsigned ShiftReg, unsigned ShiftImm, SMLoc S, in CreateShiftedRegister() argument
3645 Op->RegShiftedReg.ShiftReg = ShiftReg; in CreateShiftedRegister()
3988 << RegName(RegShiftedReg.ShiftReg) << ">"; in print()
4166 int ShiftReg = 0; in tryParseShiftRegister() local
4171 ShiftReg = SrcReg; in tryParseShiftRegister()
4206 ShiftReg = tryParseRegister(); in tryParseShiftRegister()
4207 if (ShiftReg == -1) { in tryParseShiftRegister()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 3684 unsigned ShiftReg = emitLSR_ri(MVT::i64, MVT::i64, MulReg, 32); in fastLowerIntrinsicCall() local
3686 ShiftReg = fastEmitInst_extractsubreg(VT, ShiftReg, AArch64::sub_32); in fastLowerIntrinsicCall()
3687 emitSubs_rs(VT, ShiftReg, MulReg, AArch64_AM::ASR, 31, in fastLowerIntrinsicCall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 11218 Register ShiftReg = in EmitPartwordAtomicBinary() local
11274 BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg) in EmitPartwordAtomicBinary()
11288 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg).addReg(incr).addReg(ShiftReg); in EmitPartwordAtomicBinary()
11299 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
11326 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
11368 .addReg(ShiftReg); in EmitPartwordAtomicBinary()
12224 Register ShiftReg = in EmitInstrWithCustomInserter() local
12288 BuildMI(BB, dl, TII->get(PPC::XORI), ShiftReg) in EmitInstrWithCustomInserter()
12304 .addReg(ShiftReg); in EmitInstrWithCustomInserter()
12307 .addReg(ShiftReg); in EmitInstrWithCustomInserter()
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