| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 255 int64_t ShiftImm; in matchBitfieldExtractFromSExtInReg() local
258 m_OneNonDBGUse(m_any_of(m_GAShr(m_Reg(ShiftSrc), m_ICst(ShiftImm)), in matchBitfieldExtractFromSExtInReg()
259 m_GLShr(m_Reg(ShiftSrc), m_ICst(ShiftImm)))))) in matchBitfieldExtractFromSExtInReg()
261 if (ShiftImm < 0 || ShiftImm + Width > Ty.getSizeInBits()) in matchBitfieldExtractFromSExtInReg()
264 auto Cst1 = B.buildConstant(Ty, ShiftImm); in matchBitfieldExtractFromSExtInReg()
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| H A D | AArch64InstructionSelector.cpp | 1632 Optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI); in getVectorSHLImm() local
1633 if (!ShiftImm) in getVectorSHLImm()
1636 int64_t Imm = *ShiftImm; in getVectorSHLImm()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 181 const unsigned ShiftImm = in expandAtomicCmpSwapSubword() local
185 .addImm(ShiftImm); in expandAtomicCmpSwapSubword()
188 .addImm(ShiftImm); in expandAtomicCmpSwapSubword()
557 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; in expandAtomicBinOpSubword() local
560 .addImm(ShiftImm); in expandAtomicBinOpSubword()
563 .addImm(ShiftImm); in expandAtomicBinOpSubword()
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| H A D | MipsISelLowering.cpp | 1634 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg() local
1636 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
1637 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 212 uint64_t ShiftImm, bool SetFlags = false,
216 uint64_t ShiftImm, bool SetFlags = false,
243 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
250 unsigned RHSReg, uint64_t ShiftImm);
1325 unsigned ShiftImm; in emitAddSub_ri() local
1327 ShiftImm = 0; in emitAddSub_ri()
1329 ShiftImm = 12; in emitAddSub_ri()
1358 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri()
1365 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs() argument
1375 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs()
[all …]
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| H A D | AArch64ISelDAGToDAG.cpp | 1871 uint64_t ShiftImm; in isBitfieldExtractOpFromSExtInReg() local
1872 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) && in isBitfieldExtractOpFromSExtInReg()
1873 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in isBitfieldExtractOpFromSExtInReg()
1877 if (ShiftImm + Width > BitWidth) in isBitfieldExtractOpFromSExtInReg()
1882 Immr = ShiftImm; in isBitfieldExtractOpFromSExtInReg()
1883 Imms = ShiftImm + Width - 1; in isBitfieldExtractOpFromSExtInReg()
2008 uint64_t ShiftImm; in tryBitfieldExtractOpFromSExt() local
2010 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm)) in tryBitfieldExtractOpFromSExt()
2016 unsigned Immr = ShiftImm; in tryBitfieldExtractOpFromSExt()
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| H A D | AArch64ISelLowering.cpp | 14665 unsigned ShiftImm = N->getConstantOperandVal(1); in performVectorShiftCombine() local
14666 assert(OpScalarSize > ShiftImm && "Invalid shift imm"); in performVectorShiftCombine()
14668 APInt ShiftedOutBits = APInt::getLowBitsSet(OpScalarSize, ShiftImm); in performVectorShiftCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 853 unsigned ShiftImm; // shift for OffsetReg. member
863 unsigned ShiftImm; member
875 unsigned ShiftImm; member
881 unsigned ShiftImm; member
1691 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH()
1710 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset()
1889 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift)) in isMemRegRQOffset()
2551 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
2560 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); in addRegShiftedImmOperands()
2967 Memory.ShiftImm, Memory.ShiftType); in addAddrMode2Operands()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2775 unsigned ShiftImm; in SelectShift() local
2778 ShiftImm = CI->getZExtValue(); in SelectShift()
2782 if (ShiftImm == 0 || ShiftImm >=32) in SelectShift()
2806 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 951 unsigned Size, ShiftImm; in getMVEShiftImmOpValue() local
968 ShiftImm = MI.getOperand(OpIdx).getImm(); in getMVEShiftImmOpValue()
969 return Size + ShiftImm; in getMVEShiftImmOpValue()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 666 unsigned ShiftImm = DefMI->getOperand(3).getImm(); in simplifyCode() local
669 unsigned NewElem = (SplatImm + ShiftImm) & 0x3; in simplifyCode()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 5620 const APInt &ShiftImm = N2C->getAPIntValue(); in getNode() local
5621 return getVScale(DL, VT, MulImm << ShiftImm); in getNode()
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