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Searched refs:ShTy (Results 1 – 5 of 5) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp2268 EVT ShTy = N->getOperand(1).getValueType(); in ExpandShiftByConstant() local
2276 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy)); in ExpandShiftByConstant()
2281 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy)); in ExpandShiftByConstant()
2284 DAG.getConstant(Amt, DL, ShTy)), in ExpandShiftByConstant()
2286 DAG.getConstant(-Amt + NVTBits, DL, ShTy))); in ExpandShiftByConstant()
2296 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy)); in ExpandShiftByConstant()
2304 DAG.getConstant(Amt, DL, ShTy)), in ExpandShiftByConstant()
2306 DAG.getConstant(-Amt + NVTBits, DL, ShTy))); in ExpandShiftByConstant()
2307 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy)); in ExpandShiftByConstant()
2315 DAG.getConstant(NVTBits - 1, DL, ShTy)); in ExpandShiftByConstant()
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H A DTargetLowering.cpp1483 EVT ShTy = getShiftAmountTy(InnerVT, DL); in SimplifyDemandedBits() local
1484 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) in SimplifyDemandedBits()
1485 ShTy = InnerVT; in SimplifyDemandedBits()
1488 TLO.DAG.getConstant(ShAmt, dl, ShTy)); in SimplifyDemandedBits()
H A DSelectionDAG.cpp2092 EVT ShTy = TLI->getShiftAmountTy(LHSTy, getDataLayout()); in getShiftAmountOperand() local
2093 if (OpTy == ShTy || OpTy.isVector()) return Op; in getShiftAmountOperand()
2095 return getZExtOrTrunc(Op, SDLoc(Op), ShTy); in getShiftAmountOperand()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp5409 LLT ShTy = MRI.getType(Z); in lowerFunnelShiftWithInverse() local
5422 auto Zero = MIRBuilder.buildConstant(ShTy, 0); in lowerFunnelShiftWithInverse()
5427 auto One = MIRBuilder.buildConstant(ShTy, 1); in lowerFunnelShiftWithInverse()
5436 Z = MIRBuilder.buildNot(ShTy, Z).getReg(0); in lowerFunnelShiftWithInverse()
5451 LLT ShTy = MRI.getType(Z); in lowerFunnelShiftAsShifts() local
5464 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); in lowerFunnelShiftAsShifts()
5465 ShAmt = MIRBuilder.buildURem(ShTy, Z, BitWidthC).getReg(0); in lowerFunnelShiftAsShifts()
5466 InvShAmt = MIRBuilder.buildSub(ShTy, BitWidthC, ShAmt).getReg(0); in lowerFunnelShiftAsShifts()
5472 auto Mask = MIRBuilder.buildConstant(ShTy, BW - 1); in lowerFunnelShiftAsShifts()
5475 ShAmt = MIRBuilder.buildAnd(ShTy, Z, Mask).getReg(0); in lowerFunnelShiftAsShifts()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp3639 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedRegister() argument
3643 Op->RegShiftedReg.ShiftTy = ShTy; in CreateShiftedRegister()
3653 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedImmediate() argument
3656 Op->RegShiftedImm.ShiftTy = ShTy; in CreateShiftedImmediate()